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preliminary march 17, 2003 www.ubicom.com ? 2001-2003 ubicom, inc. all rights reserved. 1 1.0 product highlights the ubicom IP2012? and ip2022? wireless network processors combine support for communication physical layer, internet protocol stack, device-speci c application, and device-speci c peripheral software modules in a single chip, and are recon gurable over the internet. they can be programmed, and reprogrammed, using pre-built software modules and con guration tools to create true single-chip solutions for a wide range of device-to-device and device-to-human communication applications. high speed communication interfaces are available via on-chip hardware serializer/deserializer (serdes) blocks. these full-duplex blocks allow the ip2022 or IP2012 to be used in a variety of communication bridging applications. each serdes block is capable of supporting 10base-t ethernet (mac and phy), usb, gpsi, spi, or uart. the high- speed operating frequency, combined with most instructions executing in a single cycle, delivers the throughput needed for emerging network connectivity applications. a flash-based program memory allows both in-system and runtime reprogramming. the ip2022 and IP2012 implement most peripheral, communications and control functions via software modules (ipmodule? software), replacing traditional hardware for maximum system design e xibility. this approach allows rapid, inexpensive product design and, when needed, quick and easy recon guration to accommodate changes in market needs or industry standards. key features: ? designed to support single-chip networked solutions ? f ast processor core ? 64kb flash program memory ? 16kb sram data/program memory ? 4kb sram data memory ? tw o serdes communication blocks supporting com- mon phys (ethernet, usb, uarts, etc.) and bridging applications (IP2012 has only one serdes unit) ? advanced risc processors ? ip2022 ? 120 and 160 mhz versions ? IP2012 ? 120 mhz version ? high speed packet processing ? instruction set optimized for communication functions ? supports software implementation of traditional hard- w are functions ? in-system reprogrammable for highest e xibility ? run time self-programmable ? vpp = vcc supply voltage figure 1-1 IP2012 / ip2022 block diagram 515-063b.eps ip2022/IP2012 10base-t ethernet (mac/phy on chip) usb 1.1 (sie on chip) gpsi spi uart/modem bluetooth hci customer application http/smtp/tftp tcp/udp ip/icmp network access layer ipmodule software phy firmware ipos operating system isp/isd interface 8-input 10-bit a/dc pll clock multiplier 5 timers external memory interface 4-kbyte data ram 16-kbyte inst./data ram 64-kbyte flash memory internet processor cpu 8/16-bit parallel slave port isa (802.11b) mini-pci/cardbus ( 802.11g/802.11a) i 2 c general-purpose i/o choices for communication: 10base-t ethernet (mac/phy on chip) usb 1.1 (sie on chip) gpsi spi uart/modem bluetooth hci host bus choices for communication: tm high-speed serial unit 1 (serdes) high-speed serial unit 2 (serdes) not available on IP2012 general purpose i/o ports IP2012 / ip2022 wireless network processors f eatures and performance optimized for network connectivity
2 www.ubicom.com IP2012 / ip2022 data sheet 1.0 product highlights 1 1.1 additional features. . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2.1 cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2.2 serializer/deserializers . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2.3 low-power support . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2.4 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2.5 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2.6 other supported functions . . . . . . . . . . . . . . . . . . . . . . .5 1.2.7 programming and debugging support . . . . . . . . . . . . . . .5 2.0 pin definitions 6 2.1 pqfp (plastic quad flat package) for ip2022. . . . . .6 2.2 pqfp (plastic quad flat package) for IP2012. . . . . .7 2.3 bga (micro ball grid array) ip2022-120 only . . . . .8 2.4 signal descriptions ? ip2022 . . . . . . . . . . . . . . . . . .9 2.5 signal descriptions ? IP2012 . . . . . . . . . . . . . . . . .12 3.0 system architecture 15 3.1 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.2 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.3 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.3.1 loading the program ram . . . . . . . . . . . . . . . . . . . . . .19 3.3.2 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 3.4 low power support . . . . . . . . . . . . . . . . . . . . . . . . .20 3.4.1 clock stop mode (sleep) . . . . . . . . . . . . . . . . . . . . . .21 3.4.2 wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 3.5 speed change . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 3.6 instruction timing . . . . . . . . . . . . . . . . . . . . . . . . . . .21 3.7 interrupt support. . . . . . . . . . . . . . . . . . . . . . . . . . . .22 3.7.1 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . .22 3.7.2 global interrupt enable bit . . . . . . . . . . . . . . . . . . . . . .25 3.7.3 interrupt latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 3.7.4 return from interrupt . . . . . . . . . . . . . . . . . . . . . . . . . .25 3.7.5 disabled interrupt resources . . . . . . . . . . . . . . . . . . . .26 3.8 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 3.8.1 brown-out detector . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.8.2 reset and interrupt vectors . . . . . . . . . . . . . . . . . . . . . .28 3.8.3 register states following reset . . . . . . . . . . . . . . . . . .28 3.9 clock oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.9.1 external connections . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.10 configuration block. . . . . . . . . . . . . . . . . . . . . . . . . .31 3.10.1 fuse0 register (not run-time programmable) . . . . . . . . .32 3.10.2 fuse1 register (not run-time programmable) . . . . . . . . .33 3.10.3 trim0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 4.0 instruction set architecture 35 4.1 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . .35 4.1.1 pointer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 4.1.2 direct addressing mode . . . . . . . . . . . . . . . . . . . . . . . .36 4.1.3 indirect addressing mode . . . . . . . . . . . . . . . . . . . . . . .36 4.1.4 indirect-with-offset addressing mode . . . . . . . . . . . . . . .37 4.2 instruction set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 4.2.1 instruction formats . . . . . . . . . . . . . . . . . . . . . . . . . . .38 4.2.2 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 4.3 instruction pipeline . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.4 subroutine call/return stack . . . . . . . . . . . . . . . . . .41 4.5 key to abbreviations and symbols . . . . . . . . . . . . . .42 4.6 instruction set summary tables. . . . . . . . . . . . . . . .42 4.7 program memory instructions. . . . . . . . . . . . . . . . . .47 4.7.1 flash timing control . . . . . . . . . . . . . . . . . . . . . . . . . .48 4.7.2 interrupts during flash operations . . . . . . . . . . . . . . . . .48 5.0 peripherals 49 5.1 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 5.1.1 port b interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 5.1.2 reading and writing the ports . . . . . . . . . . . . . . . . . . . .50 5.1.3 rxin registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 5.1.4 rxout registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 5.1.5 rxdir registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 5.1.6 inted register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 5.1.7 intf register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 5.1.8 inte register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 5.1.9 port configuration upon power-up . . . . . . . . . . . . . . . .51 5.2 timer 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 5.3 real-time timer (rttmr) . . . . . . . . . . . . . . . . . . . .52 5.4 multi-function timers (t1 and t2) . . . . . . . . . . . . . .54 5.4.1 timers t1, t2 operating modes . . . . . . . . . . . . . . . . . .54 5.4.2 t1 and t2 timer pin assignments . . . . . . . . . . . . . . . . .56 5.4.3 t1 and t2 timer registers . . . . . . . . . . . . . . . . . . . . . .56 5.5 watchdog timer (wdt) . . . . . . . . . . . . . . . . . . . . . .57 5.6 serializer/deserializer (serdes). . . . . . . . . . . . . . .58 5.6.1 serdes tx/rx buffers . . . . . . . . . . . . . . . . . . . . . . . .58 5.6.2 serdes configuration . . . . . . . . . . . . . . . . . . . . . . . . .58 5.6.3 serdes interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .59 5.6.4 protocol modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 5.6.5 10base-t ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 5.6.6 usb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 5.6.7 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 5.6.8 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 5.6.9 gpsi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 5.7 analog to digital converter (adc) . . . . . . . . . . . . . .72 5.7.1 adc reference voltage . . . . . . . . . . . . . . . . . . . . . . . .72 5.7.2 a/d converter registers . . . . . . . . . . . . . . . . . . . . . . . .72 5.7.3 using the a/d converter . . . . . . . . . . . . . . . . . . . . . . . .73 5.7.4 adc result justification . . . . . . . . . . . . . . . . . . . . . . . .73 5.8 comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 5.8.1 cmpcfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 5.9 linear feedback shift register (lfsr) . . . . . . . . . .74 5.10 parallel slave peripheral (psp) . . . . . . . . . . . . . . . .79 5.10.1 pspcfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 5.11 external memory interface (ip2022 only) . . . . . . . . .80 5.11.1 emcfg register (ip2022 only) . . . . . . . . . . . . . . . . . . .80 6.0 in-system programming 83 7.0 memory reference 84 7.0.1 registers (sorted by address) . . . . . . . . . . . . . . . . . . . .84 7.0.2 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 7.1 register bit definitions . . . . . . . . . . . . . . . . . . . . . . .89 7.1.1 adccfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 7.1.2 adctmr register . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 7.1.3 cmpcfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 7.1.4 emcfg register (ip2022 only) . . . . . . . . . . . . . . . . . . .90 7.1.5 fcfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 7.1.6 intspd register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 7.1.7 lfsra register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 7.1.8 pspcfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 7.1.9 rtcfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7.1.10 sxinte/sxintf register . . . . . . . . . . . . . . . . . . . . . . .95 7.1.11 sxmode register . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.1.12 sxrcfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.1.13 sxrcnt register . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 7.1.14 sxrsync register . . . . . . . . . . . . . . . . . . . . . . . . . . .97 7.1.15 sxsmask register . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.1.16 sxtcfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.1.17 sxtmrh/sxtmrl register . . . . . . . . . . . . . . . . . . . . . .99 7.1.18 spdreg register . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 7.1.19 status register . . . . . . . . . . . . . . . . . . . . . . . . . . .100 7.1.20 t0cfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 7.1.21 txcfg1h register . . . . . . . . . . . . . . . . . . . . . . . . . . .101 7.1.22 txcfg2h register . . . . . . . . . . . . . . . . . . . . . . . . . . .102 7.1.23 txcfg1l register . . . . . . . . . . . . . . . . . . . . . . . . . . .102 7.1.24 txcfg2l register . . . . . . . . . . . . . . . . . . . . . . . . . . .103 7.1.25 tctrl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 7.1.26 xcfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 8.0 electrical characteristics 105 8.1 absolute maximum ratings). . . . . . . . . . . . . . . . . .105 8.2 dc specifications: ip2022-120, IP2012-120 . . . . .106 8.3 dc specifications: ip2022-160. . . . . . . . . . . . . . . .108 8.4 ac specifications: ip2022-120, IP2012-120 . . . . .110 8.5 ac specifications: ip2022-160 . . . . . . . . . . . . . . . .111 8.6 comparator dc and ac specifications . . . . . . . . .112 8.7 adc 10-bit converter dc and ac specifications . .112 9.0 package dimensions 113 9.1 pqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 9.2 bga (available for ip2022-120 only) . . . . . . . . . .114 10.0 part numbering 115
IP2012 / ip2022 data sheet www.ubicom.com 3 1.1 additional features internet processor capabilities f oundation for highly flexible connectivity solution ?p erformance: 120 mips @ 120 mhz, 160 mips @ 160 mhz ? predictable execution for hard real-time applications ?f ast and deterministic 3-cycle (25ns @120mhz, 18.75ns @ 160 mhz) internal interrupt response ? hardware save/store of key registers ? functions implemented via software tightly coupled with hardware assist peripherals multiple networking protocols and physical layer support hardware ?t wo full-duplex serializer/deserializer (serdes) channels (ip2022 has two, IP2012 has one) ? flexible to support 10base-t, gpsi, spi, uart, usb protocols ? tw o channels for protocol bridging ? on-chip squelch function for 10base-t ethernet on each serdes ?f our hardware lfsr (linear feedback shift regis- ter) units ? crc generation/checking ? data whitening ? encryption memory ? 64-kbyte (32k 16) on-chip program ash memory ? 16-kbyte (8k 16) on-chip program/data ram ? 4-kbyte on-chip linear-addressed data ram ? self-programming with built-in charge pump: instruc- tions to read, write, and erase ash memory ? addresses up to 2 mbytes of external memory (ip2022 only) cpu features ? risc engine core ? ip2022-120, IP2012-120 ? dc to 120 mhz operation ? 8.33 ns instruction cycle at max frequency ? ip2022-160 ? dc to 120 mhz and 160 mhz operation only ? 6.25 ns instruction cycle at max frequency ? compact 16-bit x ed-length instructions ? single-cycle instruction execution on most instruc- tions (3 cycles for jumps and calls) ? sixteen-level hardware stack for high-performance subroutine linkage ?8 8 signed/unsigned single-cycle multiply ?p ointers and stack operation optimized for c compiler ? uniform, linear address space (no register banks) general-purpose hardware peripherals ?t wo 16-bit timers with 8-bit prescalers supporting: ? timer mode ? pwm mode ? capture/compare mode ?p arallel host interface, 8/16-bit selectable for use as a communications coprocessor (IP2012 supports 8-bit only) ? external memory interface (ip2022 only) ? one 8-bit timer with programmable 8-bit prescaler ? one 8-bit real-time clock/counter with programmable 15-bit prescaler and 32 khz crystal input ?w atchdog timer with prescaler ? 10-bit, 8-channel adc with 1/2 lsb accuracy ? analog comparator with hysteresis enable/disable ? brown-out minimum supply voltage detector ? external interrupt inputs on 8 pins (port b) sophisticated power and frequency/clock management support ? operating voltage of 2.3v to 2.7v (120 mhz) ? switching the system clock frequencies between dif- f erent clock sources ? on-chip pll clock multiplier with pre- and post-divider ? 120 mhz on-chip clock from 4.8 mhz ext. crystal ? 160 mhz on-chip clock from 3.2 mhz ext. crystal ? changing the core clock using a selectable divider ? shutting down the pll and/or the osc input ? dynamic cpu speed control with speed instruction ?p ow er-on-reset (por) logic flexible i/o ? 52 i/o pins (48 on IP2012) ? 2.3v to 3.6v symmetric cmos output drive (120mhz part) ?5 v -tolerant inputs ?p ort a pins capable of sourcing/sinking 24 ma ? optional i/o synchronization to cpu core clock re-con gurable over the internet ? customer application program updatable ? run-time self programming ? on-chip in-system programming interface ? on-chip in-system debugging support interface ? debugging at full ip2022 operating speed ? programming at device supply voltage level ? real-time emulation, program debugging, and inte- gr ated software development environment offered by leading third-party tool vendors
4 www.ubicom.com IP2012 / ip2022 data sheet 1.2 architecture 1.2.1 cpu the IP2012 and ip2022 implement an enhanced harvard architecture (i.e. separate instruction and data memories) with independent address and data buses. the 16-bit program memory and 8-bit dual-port data memory allow instruction fetch and data operations to occur in parallel. the advantage of this architecture is that instruction fetch and memory transfers can be overlapped by a multistage pipeline, so that the next instruction can be fetched from program memory while the current instruction is executed with data from the data memory. ubicom has developed a revolutionary risc-based architecture that is deterministic, jitter free, and completely reprogrammable. the architecture implements a four-stage pipeline (fetch, decode, execute, and write back). at the maximum operating frequency of 160 mhz, instructions are ex ecuted at the rate of one per 6.25 ns clock cycle. 1.2.2 serializer/deserializers one of the key elements in optimizing the IP2012 and ip2022 for device-to-device and device-to-human communication is the inclusion of on-chip serializer/deserializer units. each unit supports popular communication protocols such as gpsi, spi, uart, usb, and 10base-t ethernet, allowing the ip2000 series devices to be used in bridge, access point and gateway applications. by performing data serialization and deserialization in hardware, the cpu bandwidth needed to support serial communications is greatly reduced, especially at high baud rates. providing two units (ip2022 only) allows easy implementation of protocol conversion or bridging functions between two fast serial devices, such as usb- to-ethernet, gpsi to ethernet, or ethernet to ethernet. a single serdes unit (IP2012) provides the ability to bridge rs232, spi, or wlan (802.11b) to ethernet. 1.2.3 low-power support pa r ticular attention has been paid to minimizing power consumption. for example, an on-chip pll allows use of a lower-frequency external source (e.g., an inexpensive 4.8mhz crystal can be used to produce a 120 mhz on- chip clock; a 3.2 mhz crystal to produce a 160 mhz on- chip clock), which reduces both power consumption and emi. in addition, software can change the execution speed of the cpu to reduce power consumption, and a mechanism is provided for automatically changing the speed on entry and return from an interrupt service routine. the speed instruction speci es power-saving modes that include a clock divisor between 1 and 128. this divisor only affects the clock to the cpu core, not the timers. the speed instruction also speci es the clock source (osc1 clock, rtclk oscillator, or pll clock m ultiplier), and whether to disable the osc1 clock oscillator or the pll. the speed instruction executes using the current clock divisor. 1.2.4 memory the IP2012 / ip2022 cpu executes from a 32k 16 ash program memory and an 8k 16 ram program/data memory. in addition, the ability to write into the program ash memory allows e xible non-volatile data storage. an interface is available (ip2022 only) for up to 128k bytes of linearly addressed external memory, which can be e xpanded to 2m bytes with additional software-based i/o addressing. at 120 mhz operation, the maximum ex ecution rate is 40 mips from ash memory and 120 mips from ram. at 160 mhz operation, the maximum ex ecution rate is 53.33 mips from ash memory and 160 mips from ram. speed-critical routines can be copied from the ash memory to the ram for faster execution. the ip2000 series devices have a mechanism for in- system programming of their flash and ram program memories through a four-wire spi interface, and software has the ability to reprogram the program memories at run time. this allows the functionality of a device to be changed in the eld over the internet. 1.2.5 instruction set the ip2000 series instruction set, using 16-bit words, implements a rich set of arithmetic and logical operations, including signed and unsigned 8-bit 8-bit integer m ultiply with a 16-bit product.
IP2012 / ip2022 data sheet www.ubicom.com 5 1.2.6 other supported functions on-chip dedicated hardware also includes a pll, an 8- channel 10-bit adc, general-purpose timers, single-cycle m ultiplier, analog comparator, lfsr units, external memory interface (ip2022 only), parallel slave port, brown-out power voltage detector, watchdog timer, low- power support, multi-source wakeup capability, user- selectable clock modes, high-current outputs, and 52 general-purpose i/o pins (48 on IP2012). 1.2.7 programming and debugging support the ip2000 series has advanced in-system programming and debug support on-chip. this unobtrusive capability is provided through the isp/isd interface. there is no need f or a bond-out chip for software development. this eliminates concerns about differences in electrical characteristics between a bond-out chip and the actual chip used in the target application. designers can test and revise code on the same part used in the actual application. ubicom provides the complete red hat gnupro tools, including c compiler, assembler, linker, utilities and gnu debugger. in addition, ubicom offers an integrated gr aphical development environment which includes an editor, project manager, graphical user interface for the gnu debugger, device programmer, and ipmodule? con guration tool.
6 www.ubicom.com IP2012 / ip2022 data sheet 2.0 pin de nitions 2.1 pqfp (plastic quad flat package) for ip2022 figure 2-1 ip2022 pqfp pin de nition (top view) 515-001b.eps 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 rg3 rg2 rg1 rg0 rf7 rf6 rf5 rf4 dvdd dvss iovss iovdd rf3 rf2 rf1 rf0 re7 re6 re5 re4 re3 re2 re1 re0 tss tsck tsi tso ra0 ra1 ra2 ra3 dvdd dvss iovss iovdd rb0 rb1 rb2 rb3 rb4 rb5 rb6 rb7 rc0 rc1 rc2 rc3 ip2022/pq80-120 or ip2022/pq80-160 80 79 78 77 76 75 74 73 72 71 70 69 68 67 rst osc2 osc1 xvss xvdd rtclk2 rtclk1 dvss dvdd avss avdd rg7 rg6 66 rg4 65 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 gvdd rg5 rc4 rc5 rc6 rc7 rd0 rd1 dvdd dvss iovss iovdd rd2 rd3 rd4 rd6 rd7 rd5
IP2012 / ip2022 data sheet www.ubicom.com 7 2.2 pqfp (plastic quad flat package) for IP2012 figure 2-2 IP2012 pqfp pin de nition (top view) 515-099.eps 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 rg3 rg2 rg1 rg0 rf7 rf6 rf5 rf4 dvdd dvss iovss iovdd rf3 rf2 nc nc re7 re6 re5 re4 re3 re2 re1 re0 tss tsck tsi tso ra0 ra1 ra2 ra3 dvdd dvss iovss iovdd rb0 rb1 rb2 rb3 rb4 rb5 rb6 rb7 rc0 rc1 rc2 rc3 IP2012/pq80-120 80 79 78 77 76 75 74 73 72 71 70 69 68 67 rst osc2 osc1 xvss xvdd rtclk2 rtclk1 dvss dvdd avss avdd rg7 rg6 66 rg4 65 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 gvdd rg5 rc4 rc5 rc6 rc7 nc nc dvdd dvss iovss iovdd rd2 rd3 rd4 rd6 rd7 rd5
8 www.ubicom.com IP2012 / ip2022 data sheet 2.3 bga (micro ball grid array package) ip2022-120 only refer to section 2.4 for signal names. figure 2-3 bga pin de nition 515-092b.eps ip2022/bg80-120 1 2 3 4 5 6 7 8 9 10 a b c d e f g h j k bottom view (ball side) 1 2 3 4 5 6 7 8 9 10 a b c d e f g h j k to p view
IP2012 / ip2022 data sheet www.ubicom.com 9 2.4 signal descriptions ? ip2022 i = digital input, ai = analog input, o/do = digital output, hiz = high impedance, p = power, plp = on-chip pullup, st = schmitt trigger ta b le 2-1 signal descriptions name pin type sink @ 3.3v iovdd source @ 3.3v iovdd function pqfp bga a vdd 70 b6 p analog supply a vss 71 a6 p analog ground d vdd 9, 31, 56, 72 d1,d6, e9,g5 p logic supply d vss 10, 32, 55, 73 e1,k5, e10,d5 p logic ground gvdd 65 a8 p i/o port g supply iovdd 12, 34, 53 e5,g6, e6 p i/o supply (except port g) iovss 11, 33, 54 e2,k6, e7 p i/o ground (all ports) xvdd 76 a4 p pll supply xvss 77 d4 p pll ground osc1 78 b4 i/st clock/crystal input osc2 79 a3 o/hiz crystal output (tri-state if fuse0 bit 15 = 1) rst 80 a2 i/st/ plp reset input. there is a weak pull-up on this pin, but oating this pin does not guarantee vih. r tclk1 74 a5 i real-time clock/crystal input r tclk2 75 b5 o/hiz real-time crystal output (tri-state if fuse0 bit 14 = 1) tss 1a 1 i/st/ plp t arget spi slave select (used only for in-system pro- gr amming and debug) tsck 2 c2 i/st/ plp t arget spi clock (used only for in-system program- ming and debug) tsi 3 b1 i/st /plp t arget spi serial data input (used only for in-system programming and debug) tso 4 b2 o/hiz target spi serial data output (used only for in-sys- tem programming and debug; high z unless tss low) ra0 5 d2 i/o 24 ma 24 ma i/o port, high power output, timer 1 capture 1 input ra1 6 c1 i/o 24 ma 24 ma i/o port, high power output, timer 1 capture 2 input ra2 7 b3 i/o 24 ma 24 ma i/o port, high power output, timer 1 clock input ra3 8 e4 i/o 24 ma 24 ma i/o port, high power output, timer 1 output rb0 13 f5 i/o 8 ma 8 ma i/o port, external interrupt, timer 2 capture 1 input rb1 14 f1 i/o 8 ma 8 ma i/o port, external interrupt, timer 2 capture 2 input rb2 15 f2 i/o 8 ma 8 ma i/o port, external interrupt, timer 2 clock input
10 www.ubicom.com IP2012 / ip2022 data sheet rb3 16 g1 i/o 8 ma 8 ma i/o port, external interrupt, timer 2 output rb4 17 f4 i/o 8 ma 8 ma i/o port, external interrupt, external memory wr rb5 18 j3 i/o 8 ma 8 ma i/o port, external interrupt, parallel slave peripheral hold , external memory rd rb6 19 g2 i/o 8 ma 8 ma i/o port, external interrupt, parallel slave peripheral r/w, external memory le rb7 20 h1 i/o 8 ma 8 ma i/o port, external interrupt, parallel slave peripheral cs , external memory a0 rc0 21 j2 i/o 4 ma 4 ma i/o port, parallel slave peripheral data d8, external memory a9 rc1 22 h2 i/o 4 ma 4 ma i/o port, parallel slave peripheral data d9, external memory a10 rc2 23 j1 i/o 4 ma 4 ma i/o port, parallel slave peripheral data d10, external memory a11 rc3 24 k1 i/o 4 ma 4 ma i/o port, parallel slave peripheral data d11, external memory a12 rc4 25 k2 i/o 4 ma 4 ma i/o port, parallel slave peripheral data d12, external memory a13 rc5 26 k3 i/o 4 ma 4 ma i/o port, parallel slave peripheral data d13, external memory a14 rc6 27 j4 i/o 4 ma 4 ma i/o port, parallel slave peripheral data d14, external memory a15 rc7 28 k4 i/o 4 ma 4 ma i/o port, parallel slave peripheral data d15, external memory a16 rd0 29 g4 i/o 4 ma 4 ma i/o port, parallel slave peripheral data d0, external memory shared a1/d0 rd1 30 j5 i/o 4 ma 4 ma i/o port, parallel slave peripheral data d1, external memory shared a2/d1 rd2 35 j6 i/o 4 ma 4 ma i/o port, parallel slave peripheral data d2, external memory shared a3/d2 rd3 36 g7 i/o 4 ma 4 ma i/o port, parallel slave peripheral data d3, external memory shared a4/d3 rd4 37 k7 i/o 4 ma 4 ma i/o port, parallel slave peripheral data d4, external memory shared a5/d4 rd5 38 j7 i/o 4 ma 4 ma i/o port, parallel slave peripheral data d5, external memory shared a6/d5 rd6 39 k8 i/o 4 ma 4 ma i/o port, parallel slave peripheral data d6, external memory shared a7/d6 rd7 40 k9 i/o 4 ma 4 ma i/o port, parallel slave peripheral data d7, external memory shared a8/d7 re0 41 k10 i/o 8 ma 8 ma i/o port, s1clk - sclk (spi), rxclk (gpsi), optional serdes clock input for uart or usb. ta b le 2-1 signal descriptions (continued) name pin type sink @ 3.3v iovdd source @ 3.3v iovdd function pqfp bga
IP2012 / ip2022 data sheet www.ubicom.com 11 re1 42 h9 i/o 8 ma 8 ma i/o port, s1rxp - vp (usb), ss (spi slave), txen (gpsi master), rxen (gpsi slave) re2 43 j10 i/o 8 ma 8 ma i/o port, s1rxm - vm (usb) re3 44 j9 i/o 8 ma 8 ma i/o port, s1rxd - rcv (usb), rxd (uart), di (spi), txd (gpsi master), rxd (gpsi slave) re4 45 h10 i/o 8 ma 8 ma i/o port, s1txpe/s1oe - txd+ (ethernet), oe (usb), rxen (gpsi master), txen (gpsi slave) re5 46 g9 i/o 24 ma 24 ma i/o port, high power output, s1txp - tx+ (ethernet), vpo (usb), txd (uart), do (spi), rxd (gpsi master), txd (gpsi slave) re6 47 g10 i/o 24 ma 24 ma i/o port, high power output, s1txm - tx- (ethernet), vmo (usb), txclk/rxclk (gpsi master), txclk (gpsi slave) re7 48 j8 i/o 8 ma 8 ma i/o port, s1txme - txd- (ethernet), txbusy (gpsi) rf0 49 f7 i/o 8 ma 8 ma i/o port, s2txpe/s2oe - txd+ (ethernet), oe (usb), rxen (gpsi master), txen (gpsi slave) rf1 50 f9 i/o 24 ma 24 ma i/o port, high power output, s2txp - tx+ (ethernet), vpo (usb), txd (uart), do (spi), rxd (gpsi master), txd (gpsi slave) rf2 51 f10 i/o 24 ma 24 ma i/o port, high power output, s2txm - tx- (ethernet), vmo (usb), txclk/rxclk (gpsi master), txclk (gpsi slave) rf3 52 f6 i/o 8 ma 8 ma i/o port, s2txme - txd- (ethernet), txbusy (gpsi) rf4 57 b9 i/o 8 ma 8 ma i/o port, s2clk - sclk (spi), rxclk (gpsi), optional serdes clock input for uart or usb. rf5 58 a9 i/o 8 ma 8 ma i/o port, s2rxp - vp (usb), ss (spi slave), txen (gpsi master), rxen (gpsi slave) rf6 59 d10 i/o 8 ma 8 ma i/o port, s2rxm - vm (usb) rf7 60 d9 i/o 8 ma 8 ma i/o port, s2rxd - rcv (usb), rxd (uart), di (spi), txd (gpsi master), rxd (gpsi slave) rg0 61 c10 ai/do 4 ma* 4 ma* output port, adc0 input, comparator output rg1 62 c9 ai/do 4 ma* 4 ma* output port, adc1 input, comparator ? input rg2 63 b10 ai/do 4 ma* 4 ma* output port, adc2 input, comparator + input rg3 64 a10 ai/do 4 ma* 4 ma* output port, adc3 input, adc reference input rg4 66 b7 ai/do 4 ma* 4 ma* output port, adc4 input, s1rx- rg5 67 b8 ai/do 4 ma* 4 ma* output port, adc5 input, s1rx+ rg6 68 a7 ai/do 4 ma* 4 ma* output port, adc6 input, s2rx- rg7 69 d7 ai/do 4 ma* 4 ma* output port, adc7 input, s2rx+ * gvdd = 2.5v ta b le 2-1 signal descriptions (continued) name pin type sink @ 3.3v iovdd source @ 3.3v iovdd function pqfp bga
12 www.ubicom.com IP2012 / ip2022 data sheet 2.5 signal descriptions ? IP2012 i = digital input, ai = analog input, o/do = digital output, hiz = high impedance, p = power, plp = on-chip pullup, st = schmitt trigger ta b le 2-2 signal descriptions name pin type sink @ 3.3v iovdd source @ 3.3v iovdd function pqfp bga a vdd 70 b6 p analog supply a vss 71 a6 p analog ground d vdd 9, 31, 56, 72 d1,d6, e9,g5 p logic supply d vss 10, 32, 55, 73 e1,k5, e10,d5 p logic ground gvdd 65 a8 p i/o port g supply iovdd 12, 34, 53 e5,g6, e6 p i/o supply (except port g) iovss 11, 33, 54 e2,k6, e7 p i/o ground (all ports) xvdd 76 a4 p pll supply xvss 77 d4 p pll ground osc1 78 b4 i/st clock/crystal input osc2 79 a3 o/hiz crystal output (tri-state if fuse0 bit 15 = 1) rst 80 a2 i/st/ plp reset input. there is a weak pull-up on this pin, but oating this pin does not guarantee vih. r tclk1 74 a5 i real-time clock/crystal input r tclk2 75 b5 o/hiz real-time crystal output (tri-state if fuse0 bit 14 = 1) tss 1a 1 i/st/ plp t arget spi slave select (used only for in-system pro- gr amming and debug) tsck 2 c2 i/st/ plp t arget spi clock (used only for in-system program- ming and debug) tsi 3 b1 i/st /plp t arget spi serial data input (used only for in-system programming and debug) tso 4 b2 o/hiz target spi serial data output (used only for in-sys- tem programming and debug; high z unless tss low) ra0 5 d2 i/o 24 ma 24 ma i/o port, high power output, timer 1 capture 1 input ra1 6 c1 i/o 24 ma 24 ma i/o port, high power output, timer 1 capture 2 input ra2 7 b3 i/o 24 ma 24 ma i/o port, high power output, timer 1 clock input ra3 8 e4 i/o 24 ma 24 ma i/o port, high power output, timer 1 output rb0 13 f5 i/o 8 ma 8 ma i/o port, external interrupt, timer 2 capture 1 input rb1 14 f1 i/o 8 ma 8 ma i/o port, external interrupt, timer 2 capture 2 input rb2 15 f2 i/o 8 ma 8 ma i/o port, external interrupt, timer 2 clock input
IP2012 / ip2022 data sheet www.ubicom.com 13 rb3 16 g1 i/o 8 ma 8 ma i/o port, external interrupt, timer 2 output rb4 17 f4 i/o 8 ma 8 ma i/o port, external interrupt rb5 18 j3 i/o 8 ma 8 ma i/o port, external interrupt, parallel slave peripheral hold rb6 19 g2 i/o 8 ma 8 ma i/o port, external interrupt, parallel slave peripheral r/w rb7 20 h1 i/o 8 ma 8 ma i/o port, external interrupt, parallel slave peripheral cs rc0 21 j2 i/o 4 ma 4 ma i/o port, parallel slave peripheral data d8 rc1 22 h2 i/o 4 ma 4 ma i/o port, parallel slave peripheral data d9 rc2 23 j1 i/o 4 ma 4 ma i/o port, parallel slave peripheral data d10 rc3 24 k1 i/o 4 ma 4 ma i/o port, parallel slave peripheral data d11 rc4 25 k2 i/o 4 ma 4 ma i/o port, parallel slave peripheral data d12 rc5 26 k3 i/o 4 ma 4 ma i/o port, parallel slave peripheral data d13 rc6 27 j4 i/o 4 ma 4 ma i/o port, parallel slave peripheral data d14 rc7 28 k4 i/o 4 ma 4 ma i/o port, parallel slave peripheral data d15 rd2 35 j6 i/o 4 ma 4 ma i/o port rd3 36 g7 i/o 4 ma 4 ma i/o port rd4 37 k7 i/o 4 ma 4 ma i/o port rd5 38 j7 i/o 4 ma 4 ma i/o port rd6 39 k8 i/o 4 ma 4 ma i/o port rd7 40 k9 i/o 4 ma 4 ma i/o port re0 41 k10 i/o 8 ma 8 ma i/o port, s1clk - sclk (spi), rxclk (gpsi), optional serdes clock input for uart or usb. re1 42 h9 i/o 8 ma 8 ma i/o port, s1rxp - vp (usb), ss (spi slave), txen (gpsi master), rxen (gpsi slave) re2 43 j10 i/o 8 ma 8 ma i/o port, s1rxm - vm (usb) re3 44 j9 i/o 8 ma 8 ma i/o port, s1rxd - rcv (usb), rxd (uart), di (spi), txd (gpsi master), rxd (gpsi slave) re4 45 h10 i/o 8 ma 8 ma i/o port, s1txpe/s1oe - txd+ (ethernet), oe (usb), rxen (gpsi master), txen (gpsi slave) re5 46 g9 i/o 24 ma 24 ma i/o port, high power output, s1txp - tx+ (ethernet), vpo (usb), txd (uart), do (spi), rxd (gpsi master), txd (gpsi slave) re6 47 g10 i/o 24 ma 24 ma i/o port, high power output, s1txm - tx- (ethernet), vmo (usb), txclk/rxclk (gpsi master), txclk (gpsi slave) re7 48 j8 i/o 8 ma 8 ma i/o port, s1txme - txd- (ethernet), txbusy (gpsi) rf2 51 f10 i/o 24 ma 24 ma i/o port, high power output ta b le 2-2 signal descriptions (continued) name pin type sink @ 3.3v iovdd source @ 3.3v iovdd function pqfp bga
14 www.ubicom.com IP2012 / ip2022 data sheet rf3 52 f6 i/o 8 ma 8 ma i/o port rf4 57 b9 i/o 8 ma 8 ma i/o port rf5 58 a9 i/o 8 ma 8 ma i/o port rf6 59 d10 i/o 8 ma 8 ma i/o port rf7 60 d9 i/o 8 ma 8 ma i/o port rg0 61 c10 ai/do 4 ma* 4 ma* output port, adc0 input, comparator output rg1 62 c9 ai/do 4 ma* 4 ma* output port, adc1 input, comparator ? input rg2 63 b10 ai/do 4 ma* 4 ma* output port, adc2 input, comparator + input rg3 64 a10 ai/do 4 ma* 4 ma* output port, adc3 input, adc reference input rg4 66 b7 ai/do 4 ma* 4 ma* output port, adc4 input, s1rx- rg5 67 b8 ai/do 4 ma* 4 ma* output port, adc5 input, s1rx+ rg6 68 a7 ai/do 4 ma* 4 ma* output port, adc6 input rg7 69 d7 ai/do 4 ma* 4 ma* output port, adc7 input * gvdd = 2.5v ta b le 2-2 signal descriptions (continued) name pin type sink @ 3.3v iovdd source @ 3.3v iovdd function pqfp bga
IP2012 / ip2022 data sheet www.ubicom.com 15 3.0 system architecture the IP2012 / ip2022 cpus execute from a 32k 16 ash program memory and an 8k 16 ram program memory. figure 3-1 shows the ip2022 detailed block diagram, and figure 3-2 shows the IP2012 detailed block diagram. at 120 mhz operation, the maximum execution rate is 40 mips from flash and 120 mips from ram. at 160 mhz operation, the maximum execution rate is 53.33 mips from flash and 160 mips from ram. speed-critical routines can be copied from the ash memory to the ram f or faster execution. the cpu operates on 8-bit data in 128 special-purpose registers, 128 global registers, and 3840 bytes of data memory. the special-purpose registers hold control and status bits used for cpu control and for interface with hardware peripherals (timers, i/o ports, a/d converter, etc.)although the philosophy followed in the design of ubicom products emphasizes the use of fast risc cpus with predictable execution times to emulate peripheral devices in software (the ipmodule? concept), there are a fe w hardware peripherals which are dif cult to emulate in software alone (e.g. an a/d converter) or consume an e xcessive number of instruction cycles when operating at high speed (e.g. data serialization/deserialization). the design of the IP2012 / ip2022 incorporates only those hardware peripherals which can greatly accelerate or e xtend the reach of the ipmodule? concept. the hardware peripherals included on-chip are: ? 52 i/o port pins (48 on IP2012) ?w atchdog timer ? real-time timer ?2 multifunction 16-bit timers with compare and cap- ture registers ?2 real-time 8-bit timers ?2 serializer/deserializer (serdes) units (IP2012 has one unit) ?4 linear feedback shift register (lfsr) units ? 10-bit, 8-channel a/d converter ? analog comparator ?p arallel slave peripheral interface ? external sram interface (ip2022 only) there is a single interrupt vector which can be reprogrammed by software. on-chip peripherals and up to 8 external inputs can raise interrupts. there are ve sources of reset: ? rst external reset input ?p ow er-on reset (por) logic ? brown-out reset (bor) logic (detects low avdd con- dition) ?w atchdog timer reset ? in-system debugging/programming interface reset an on-chip pll clock multiplier (x50) enables high-speed operation (up to 160 mhz) from a slow-speed external figure 3-1 ip2022 detailed block diagram internal data bus port a rtclk sxclk real-time clock driver osc driver timer 1 (t1) port e port f port g (2) serializer/ deserializers analog comparator, 2x ethernet squelch timer 2 (t2) port b timer 0 (t0) interrupt port d port c edge det. parallel 8/16-bit slave peripheral adc multiplexer divider cpu core clock multiplexer divider pll divider divider 4kb data memory 515-038b.eps system clock real-time timer reset w alu watchdog timer with pre-scaler isd writeback isp brown out por rst execute decode 64kb flash program memory 16kb ram program memory fetch internal rc clock (4) lfsr units ext. memory interface
16 www.ubicom.com IP2012 / ip2022 data sheet clock input or crystal. a cpu clock-throttling mechanism allows ne control over power consumption in modes that do not require maximum speed, such as waiting for an interrupt. the ip200 series has a mechanism for in-system programming of its ash and ram program memories through a four-wire spi interface. this provides easy programming and reprogramming of devices on assembled circuit boards. in addition, the ash memory can be programmed by software at run time, for example to store user-speci c data such as phone numbers and to receive software upgrades downloaded over the internet. the devices also have an on-chip debugging facility which makes the internal operation of the chip visible to third- party debugging tools. 3.1 cpu registers figure 3-3 shows the cpu registers, which consist of seven 8-bit registers, seven 16-bit registers, and one 24- bit register. the 16-bit registers are formed from pairs of 8-bit registers, and the 24-bit register is formed from three 8-bit registers. for the register quick reference guide, see section 7.0 and section 7.1. the w or working register is used as the source or destination for most arithmetic, movement, and logical instructions. the status register holds the condition ags for the results of arithmetic and logical operations, the page bits (used for jumps and subroutine calls), and bits which indicate the skipping state of the core and control of continuation skip after return from interrupt. figure 3-4 shows the assignment of the bits in the status register. figure 3-2 IP2012 detailed block diagram internal data bus port a rtclk sxclk real-time clock driver osc driver timer 1 (t1) port e port f port g (1) serializer/ deserializer analog comparator, 2x ethernet squelch timer 2 (t2) port b timer 0 (t0) interrupt port d port c edge det. parallel 8-bit slave peripheral adc multiplexer divider cpu core clock multiplexer divider pll divider divider 4kb data memory 515-100.eps system clock real-time timer reset w alu watchdog timer with pre-scaler isd writeback isp brown out por rst execute decode 64kb flash program memory 16kb ram program memory fetch internal rc clock (4) lfsr units
IP2012 / ip2022 data sheet www.ubicom.com 17 . ? p a2:pa0 ?program memory page select bits. used to e xtend the 13-bit address encoded in jump and call in- structions (selects 8k-word pages). modi ed using the page instruction. ? sar ?skip after return bit. this bit should be set if the core should be in the skipping state, and should not be set if the core should not be in the skipping state after the completion of the return instruction ( ret , retnp , or retw instructions, but not reti ). the return instruction will also clear the sar control bit to ensure correct behavior after the dynamic jump. ? ssf ?shadowed skipping/not state flag. gives the isr the ability to know if the interrupt occurred imme- diately following a skip instruction. the software can choose either to clear the ssf ag in the isr or to make the rst instruction of the context switching code a nop to ush out the skip state. ? z ?zero bit. affected by most logical, arithmetic, and data movement instructions. set if the result was zero, otherwise cleared. ? dc ?digit carry bit. after addition, set if carry from bit 3 occurred, otherwise cleared. after subtraction, cleared if borrow from bit 3 occurred, otherwise set. ? c ?carry bit. after addition, set if carry from bit 7 of the result occurred, otherwise cleared. after subtrac- tion, cleared if borrow from bit 7 of the result occurred, otherwise set. after rotate ( rr or rl ) instructions, loaded with the lsb or msb of the operand, respec- tively. the mulh register receives the upper 8 bits of the 16-bit product from signed or unsigned multiplication. the lower 8 bits are loaded into the w register. the spdreg register holds bits that control the cpu speed and clock source settings, and is loaded by using the speed instruction, as shown in figure 3-5. the spdreg register is read-only, and its contents may only be changed by executing a speed instruction, taking an interrupt, or returning from an interrupt. for more information about the speed instruction and the clock throttling mechanism, see section 3.4 and figure 3-17. note: the speed instruction should be followed by a nop instruction if port b interrupt is used to wake up from sleep mode. ? pll ?enable x50 pll clock multiplier; 0 = enabled; 1 = disabled. power consumption can be reduced by disabling it. see figure 3-17. ? osc ?enable osc oscillator; 0 = enabled; 1 = dis- abled (stops osc oscillator and blocks propagation of osc1 external clock input). power consumption can be reduced by disabling it. ? clk1:0 ?selects the system clock source, as shown in table 3-1. see figure 3-17 for the clock logic. see section 7.1.5 (fcfg register, frdts1:0 bits) for ex- ceptions. figure 3-3 cpu registers 76543210 p a2:0 sar ssf z dc c figure 3-4 status register intvech/intvecl register * w register status register mulh register spdreg register iph/ipl register dph/dpl register sph/spl register datah/datal register * addrx/addrh/addrl register 515-040b.eps ipch/ipcl register * 7 15 0 0 interrupt registers 15 0 pointer registers 15 0 program memory/external memory interface registers pch/pcl register 15 xcfg register intspd register addrsel register 23 7 * low byte doesn't carry to high byte 76543 0 pll osc clk1:0 cdiv3:0 figure 3-5 spdreg register
18 www.ubicom.com IP2012 / ip2022 data sheet ? cdiv3:0 ?selects the clock divisor used to generate the cpu core clock from the system clock, as shown in table 3-2 (also see figure 3-17). the intspd register holds bits that control the cpu speed and clock source during interrupt service routines (it is copied to the spdreg register when an interrupt occurs). it has the same format as the spdreg register. when the osc crystal driver is stopped (spdreg bit 6 = 1) and port b or real time timer interrupts are enabled, then intspd bits 5 and 4 must not both be 0, because the crystal startup time plus pll startup time may be greater than wudp2:0 (see figure 3-17). the xcfg register holds additional control and status bits, as shown in figure 3-6. ? gie ?global interrupt enable bit. when set, interrupts are enabled. when clear, interrupts are disabled. for more information about interrupt processing, see section 3.7. ? fwp ? ash write protect bit. when clear, writes to ash memory are ignored. for more information about programming the ash memory, see section 4.7. ? r teos ?real-time timer oversampling enable bit. when set, oversampling is used. for more informa- tion, see section 5.3. ? r t osc_en ?rtclk oscillator enable bit. when clear, the rtclk oscillator is operational. when set, the rtclk oscillator is turned off. ? int_en ? int instruction interrupt enable bit. when set, int instructions cause interrupts. when clear, int instructions only increment the pc, like nop . ? fbusy ?read-only ash memory busy bit. set while f etching instructions out of ash memory or while b usy processing an iread , ireadi , iwrite , iwritei , fwrite , fread or ferase instruction that operates on flash, otherwise clear. for more in- fo r mation about programming the ash memory, see section 4.7. the pch and pcl register pair form a 16-bit program counter. the pch register is read-only. the pcl register can be used to implement a lookup table, by moving a va r iable to the w register, then executing an add pcl,w instruction. if w=01 when the add occurs, the instruction after the add will be skipped; if w=02, two instructions will be skipped, etc. the ipch and ipcl register pair speci es the return address when a reti instruction is executed. the intvech and intvecl register pair speci es the interrupt vector. it has a default value of 0 following reset. on a return from interrupt, an option of the reti instruction allows software to save the incremented value of the program counter in the intvech and intvecl registers. the iph and ipl register pair is used as a pointer for indirect addressing. for more information about indirect addressing, see section 4.1.3. the dph and dpl register pair and the sph and spl register pair are used as pointer registers for indirect-with- offset addressing. for more information about indirect- ta b le 3-1 clk1:0 field encoding clk1:0 system clock source 00 pll clock multiplier 01 osc oscillator/external osc1 input 10 rtclk oscillator/external clock on r tclk1 input 11 system clock off ta b le 3-2 system clock divisor cdiv3:0 system clock divisor cpu core frequency 120 mhz sys- tem clock 160 mhz sys- tem clock 0000 1 120 mhz 160 mhz 0001 2 60 mhz 80 mhz 0010 3 40 mhz 53.33 mhz 0011 4 30 mhz 40 mhz 0100 5 24 mhz 32 mhz 0101 6 20 mhz 26.66 mhz 0110 8 15 mhz 20 mhz 0111 10 12 mhz 16 mhz 1000 12 10 mhz 13.33 mhz 1001 16 7.5 mhz 10 mhz 1010 24 5 mhz 6.66 mhz 1011 32 3.75 mhz 5 mhz 1100 48 2.5 mhz 3.33 mhz 1101 64 1.875 mhz 2.5 mhz 1110 128 0.9375 mhz 1.25 mhz 1111 clock off 0 mhz 0 mhz 76 5 4 3 21 0 gie fwp r teos r t osc_en int_en rsvd fbusy figure 3-6 xcfg register
IP2012 / ip2022 data sheet www.ubicom.com 19 with-offset addressing, see section 4.1.4. the sph and spl registers are automatically post-decremented when storing to memory with a push instruction, and they are automatically pre-incremented when reading from memory with a pop instruction. the addrsel register holds an index to one of eight 24- bit pointers used to address program memory. the current program memory/external memory 24-bit address selected by the addrsel register is accessible in the addrx (bits 23:16), addrh (bits 15:8), and addrl (bits 7:0) registers. the upper 5-bits of the addrsel register are unused. all 8 banks of 24-bits are initialized to 0x000000 upon reset. program memory is always read or written as 16-bit w ords. on reads, the data from program memory is loaded into the datah and datal register pair. on writes, the contents of the datah and datal register pair are loaded into the program memory. 3.2 data memory figure 3-7 is a map of the data memory. the special- purpose registers and the rst 128 data memory locations (between addresses 0x080 and 0x0ff) can be accessed with a direct addressing mode in which the absolute address of the operand is encoded within the instruction. the remaining 3840 bytes of data memory (between addresses 0x100 and 0xfff) must be accessed using indirect or indirect-with-offset addressing modes. there is one 16-bit register for the indirect address pointer, and two 16-bit registers for indirect-with-offset address pointers. the offset is a 7-bit value encoded within the instruction. f or more information about the addressing modes, see section 4.1. figure 3-7 data memory map 3.3 program memory figure 3-8 is a map of the program memory. a program memory address in the intvech/invecl, ipch/ipcl, or pch/pcl registers or on the hardware stack is a word address. however, the gnu software tools require byte addresses when referring to locations in program memory. an address loaded in the addrx/addrh/addl register is a byte address. the program memory is organized as 8k-word pages (16k bytes). single-instruction jumps and subroutine calls are restricted to be within the same page. longer jumps and calls require using a page instruction to load the upper address bits into the pa2:0 bits of the status register. the page instruction must immediately precede the jump or call instruction. the pa2:0 bits should not be modi ed by writing directly to the status register, because this may cause a mismatch between the pa2:0 bits in the status register and the current program counter (see section 3.3.2). for more information about the ash program memory, see section 4.7 and section 7.0.2. figure 3-8 program memory map external memory is not shown in figure 3-8 because the cpu cannot execute instructions directly out of external memory. for more information about external memory, see section 5.11. 3.3.1 loading the program ram software loads the program ram from program ash memory using the iread / ireadi and iwrite / iwritei instructions. the iread instruction reads the 16-bit word speci ed by the address held in the addrx/addrh/addrl register. this word can be in program ash memory, program ram, or external memory. when the iread instruction is executed, bits 515-028a.eps 127 special-purpose registers 3840 bytes data memory 0x001 70 0x080 0xfff 128 global registers 0x100 0x07f 0x0ff 515-006b.eps program ram reserved (undefined data) 0x000000 15 0 0x004000 flash program memory 0x014000 flash program memory 0x018000 flash program memory 0x01c000 flash program memory 0x01fffe 0x010000 0x0000 0x2000 0xa000 0xc000 0xe000 0xffff 0x8000 byte address word address 0x003ffe 0x013ffe 0x017ffe 0x01bffe 0x00fffe 0x1fff 0x9fff 0xbfff 0xdfff 0x7fff
20 www.ubicom.com IP2012 / ip2022 data sheet 15:8 of the word are loaded into the datah register, and bits 7:0 are loaded into the datal register. the address is a word-aligned byte address (i.e. an address that is zero in its lsb). the ireadi instruction is identical to the iread instruction, except that it also increments the address by 2. the iwrite instruction writes the 16-bit word held in the d at ah/datal registers to the program ram location speci ed by the address held in the addrx/addrh/addrl register. the iwritei instruction is identical, except that it also increments the address by 2. for more information about the iread / ireadi and iwrite / iwritei instructions, see section 4.7. 3.3.2 program counter the program counter holds the 16-bit address of the instruction to be executed. the lower eight bits of the program counter are held in the pcl register, and the upper eight bits are held in the pch register. a write to the pcl register will cause a jump to the 16-bit address speci ed by the pch and pcl registers. if the pcl register is written as the destination of an add or addc instruction and carry occurs, the pch register is automatically incremented. (this may cause a mismatch between the pa2:0 bits in the status register and the current program counter, therefore it is strongly recommended that direct modi cation of the pcl register is only used for jumps within a page.) the pch register is read-only. the pa2:0 bits in the status register are not used for address generation, except when a jump or subroutine call instruction is executed. however, when an interrupt is taken, the pa2:0 bits are automatically updated with the upper three bits of the interrupt vector (intvech/l). these bits are restored from the status shadow register when the interrupt service routine returns (i.e. executes a reti instruction). 3.4 low power support software can change the execution speed of the cpu to reduce power consumption. a mechanism is also provided for automatically changing the speed on entry and return from the interrupt service routine. the speed instruction speci es power-saving modes that include a clock divisor between 1 and 128. this divisor only affects the clock to the cpu core, not the timers, serdes, e xternal memory or adc (see figure 3-17). the speed instruction also speci es the clock source (osc clock, r tclk oscillator, or pll clock multiplier) and whether to disable the osc clock oscillator or the pll. f or maximum power savings when running from the osc clock, disable the rtclk oscillator (r t osc_en bit in the xcfg register), disable the watchdog timer (wdte bit in the fuse1 register), disable the a/d converter (adcgo bit in the adccfg register, disable the analog comparator (cmpen bit in the cmpcfg register) and check that no ash operation is in progress (fbusy bit in the xcfg register) before executing a speed #$ff instruction. to summarize settings for lowest power: ? xcfg bit 4 = 1 ? fuse1 bit 3 = 0 ? cmpcfg bit 7 = 0 ? adccfg bit 3 = 0 ? xcfg bit 0 = 0 note: before executing the speed instruction or ex ecuting an interrupt (an interrupt will cause intspd to be copied to spdreg), insure that the fcfg register has appropriate settings for the new clock frequency. the spdreg register (see figure 3-5) holds the current settings for the clock divisor, clock source, and disable bits. these settings can be explicitly changed by ex ecuting a speed instruction, and they change automatically on interrupts. the spdreg register is read- only, and its contents may only be changed by executing a speed instruction, taking an interrupt, or returning from an interrupt. two consecutive speed instructions are not allowed. the intspd register speci es the settings used during execution of the interrupt service routine. the intspd register is both readable and writable. on return from interrupts, the reti instruction includes a bit that speci es whether the pre-interrupt speed is restored or the current speed is maintained (see table 3- 5). the actual speed of the cpu is indicated by the spdreg register unless the speci ed speed is faster than the ash access time and the program is executing out of ash. when program execution moves from program ram to program ash memory, the new clock divisor will be the g reater (slower) of the clock divisor indicated by the spdreg register and the clock divisor required to avoid violating the ash memory access time. the spdreg register does not indicate if the ash clock divisor is being used. the speed indicated by the spdreg will be ov erridden only if the speed is too fast for the ash memory. the fcfg register holds bits that specify the minimum n umber of system clock cycles for each ash memory cycle (see section 4.7.1).
IP2012 / ip2022 data sheet www.ubicom.com 21 3.4.1 clock stop mode (sleep) when a speed instruction occurs, it is possible for the cpu clock source to be disabled. the clock to the cpu core may be disabled while the system clock is left r unning, or the system clock may be disabled which also disables the cpu core clock. see spdreg, section 7.1.18. 3.4.2 wakeup recovery from sleep (core clock stop) mode to normal ex ecution is possible from these sources: ? external interrupts (i.e. port b interrupts) ? real-time timer interrupts ?w atchdog timer over ow reset ? brown-out voltage reset ? rst external reset the rst two sources listed do not reset the chip, so register and cpu states are maintained. the last three sources reset the chip, so software must perform all of its reset initialization tasks to recover. this usually requires additional time, as compared to recovery through an interrupt. if a port b or real time timer interrupt occurs during core clock stop mode, the intspd register will be copied to the spdreg register, the isr will be executed, then mainline code will resume execution at the instruction after the speed command that caused the clock to stop. note: if wakeup triggers an isr that has a reti instruction which reinstates the pre-interrupt speed (see ta b le 3-5), the device goes back to sleep. if a subsequent wa k eup occurs which does not reinstate the pre-interrupt speed, then a nop m ust be inserted after the speed instruction which puts it to sleep. 3.5 speed change the speed instruction executes using the current clock divisor. the new clock divisor takes effect with the f ollowing instruction, as shown in the following code e xample. the automatic speed changes require a certain amount of delay to take effect (see figure 3-5 and figure 3-17): ? changing the core clock divisor ?there is no delay when the clock divisor is changed (the instruction af- ter the speed instruction is executed at the new speed). ? changing the system clock source ?the delay is up to one cycle of the slower clock. for example, chang- ing between 4 mhz and 120 mhz could require up to 0.25 microseconds. ? tu r ning on the osc clock oscillator (clearing the osc bit in the spdreg register) ?the system clock suspend time is speci ed in the wudx2:0 bits in the fuse0 register (see section 3.10.1). ? tu r ning on the pll clock multiplier (clearing the pll bit in the spdreg register) ?the system clock sus- pend time is speci ed in the wudp2:0 bits in the fuse0 register. if both the osc oscillator and pll are re-enabled simultaneously, the delay is controlled by only the wudp2:0 bits. bits in the fuse0 register are flash memory cells which cannot be changed dynamically during program execution. 3.6 instruction timing all instructions that perform branches take 3 cycles to complete, consisting of 1 cycle to execute and 2 cycles to load the pipeline. in the case of an automatic speed change, the execution time will be with respect to the original speed and the pipeline load time will be with respect to the new speed. conditional branching is implemented in the IP2012 / ip2022 by using conditional skip instructions to branch ov er an unconditional jump instruction. to support conditional branching to other pages, the conditional skip instructions will skip over two instructions if the rst instruction is a page instruction. the loadh and loadl instructions also cause an additional instruction to be skipped. when any of these conditions occur, it is called an e xtended skip instruction . nop ;assume divisor is 4, so this ;instruction takes 4 cycles speed #0x06 ;change the divisor to 8, ;instruction takes 4 cycles nop ;instruction takes 8 cycles speed #0x00 ;change the divisor to 1, ;instruction takes 8 cycles nop ;instruction takes 1 cycle ta b le 3-3 branch timing instruction execution time pipeline load time jmp 12 call 12 ret 12 reti 12
22 www.ubicom.com IP2012 / ip2022 data sheet skip instructions take 1 cycle if they do not skip, or 2 cycles if they skip over one instruction. an extended skip instruction may skip over more than one loadh , loadl , or page instruction, however this operation is interruptible and does not affect interrupt latency. the iread and iwrite instructions take 4 cycles. the m ultiply instructions take 1 cycle. 3.7 interrupt support there are three types of interrupt sources: ? on-chip peripherals ?the serializer/deserializer units, real-time timer, timer 0, timer 1, and timer 2 are capa- b le of generating interrupts. the parallel slave periph- eral does not generate interrupts on its own; it requires programming one of the port b external inter- r upt inputs to generate interrupts on its behalf. ? external interrupts ?the eight pins on port b can be programmed to generate interrupts on either rising or f alling edges (see section 5.1.1). ? int instruction ?the int instruction can be executed by software to generate an interrupt. the int_en bit can be considered as the interrupt ag for the int in- struction, if the isr checks for interrupt source. the int_en bit in the xcfg register must be set to enable the int instruction to trigger an interrupt. because the reti instruction returns to the int instruction, the int_en bit must be cleared in the interrupt ser- vice routine (isr) before returning. figure 3-9 shows the system interrupt logic. each interrupt source has an interrupt enable bit. to be capable of generating an interrupt, the interrupt enable bit and the global interrupt enable (gie) bit must be set. figure 3-9 system interrupt logic 3.7.1 interrupt processing there is one interrupt vector held in the intvech and intvecl registers, which is reprogrammable by software. when an interrupt is taken, the current pc is saved in the ipch and ipcl registers. on return from interrupt (i.e. execution of the reti instruction), the pc is restored from the ipch and ipcl registers. optionally, the reti instruction may also copy the incremented pc to the intvech and intvecl registers before returning. this has the effect of loading the intvech and intvecl registers with the address of the next instruction following the reti instruction. this option can be used to directly implement a state machine, such as a simple round-robin scheduling mechanism for a series of interrupt service routines (isrs) in consecutive memory locations. if multiple sources of interrupts have been enabled, the isr must check the interrupt ags of each source to determine the cause of the interrupt. the isr must clear the interrupt ag for the source of the interrupt to prevent retriggering of the interrupt on completion of the isr (i.e. ex ecution of the reti instruction). because the interrupt logic adds a 2-cycle delay between clearing an interrupt ag and deasserting the interrupt request to the cpu, the ag must be cleared at least 2 cycles before the reti instruction is taken. when an interrupt is taken, the registers shown in figure 3-10 are copied to a shadow register set. each shadow register is actually a 2-level push-down stack, so one level of interrupt nesting is supported in hardware. the interrupt processing mechanism is completely independent of the 16-level call/return stack used for subroutines. the contents of the datah and datal registers are pushed to their shadow registers 4 cycles after the interrupt occurs, to protect the result of any pending iread instruction. therefore, software should not access the datah or datal registers during the rst instruction of an isr. 515-067c.eps interrupt to cpu port b interrupt serdes interrupt timer 0 t0if bit real-time timer rtif bit timer 1 ofif bit timer 1 cap2if/cmp2if bit timer 1 cap1if bit timer 1 cmp1if bit timer 2 ofif bit int instruction gie bit int_en bit t imer 2 cap2if/cmp2if bit t imer 2 cap1if bit t imer 2 cmp1if bit
IP2012 / ip2022 data sheet www.ubicom.com 23 figure 3-10 interrupt processing (on entry to the isr) note: on entry to the isr the w, mulh, iph/ipl, dph/dpl, sph/spl, addrsel and datah/datal register values don?t change from their mainline code values (they are copied to their shadow registers). intvech/intvecl register w register status register mulh register iph/ipl register dph/dpl register sph/spl register datah/datal register 515-068d.eps w shadow register 1 status shadow register 1 mulh shadow register 1 iph/ipl shadow register 1 dph/dpl shadow register 1 sph/spl shadow register 1 datah/datal shadow register 1 ipch/ipcl register pc w shadow register 2 status shadow register 2 mulh shadow register 2 iph/ipl shadow register 2 dph/dpl shadow register 2 sph/spl shadow register 2 datah/datal shadow register 2 intspd register spdreg register spdreg shadow register 1 spdreg shadow register 2 ipch/ipcl shadow register intvech bits 7:5 copied gie xcfg bit 7 gie shadow bit 1 gie shadow bit 2 gie = 0
24 www.ubicom.com IP2012 / ip2022 data sheet on return from the isr, these registers are restored from the shadow registers, as shown in figure 3-11. figure 3-11 interrupt return processing (upon execution of reti) ipch/ipcl register w register status register mulh register w shadow register 1 status shadow register 1 mulh shadow register 1 iph/ipl register dph/dpl register sph/spl register datah/datal register iph/ipl shadow register 1 dph/dpl shadow register 1 sph/spl shadow register 1 datah/datal shadow register 1 515-069c.eps pc intvech/intvecl register pc + 1 if reti instruction bit 1 is set w shadow register 2 status shadow register 2 mulh shadow register 2 iph/ipl shadow register 2 dph/dpl shadow register 2 sph/spl shadow register 2 datah/datal shadow register 2 spdreg register if reti instruction bit 2 is set spdreg shadow register 1 spdreg shadow register 2 t0tmr register t0tmr + w if reti instruction bit 0 is set gie xcfg bit 7 gie shadow bit 1 gie shadow bit 2 ipch/ipcl shadow
IP2012 / ip2022 data sheet www.ubicom.com 25 3.7.2 global interrupt enable bit the gie bit serves two purposes: ? preventing an interrupt in a critical section of mainline code ? supporting nested interrupts the gie bit is automatically cleared when an interrupt occurs, to disable interrupts while the isr is executing. the gie bit is automatically set by the reti instruction to re-enable interrupts when the isr returns. to re-enable interrupts during isr execution, the isr code must rst clear the source of the rst interrupt. it may also be desirable to disable speci c interrupts before setting the gie bit to provide interrupt prioritization. even with gie deasserted, interrupt triggers are still captured b ut an interrupt won?t be triggered until gie is re-enabled. caution must be taken not to exceed the interrupt shadow register stack depth of 2. clearing the gie bit in the isr cannot be used to globally disable interrupts so that they remain disabled when the isr returns, because the reti instruction automatically sets the gie bit. to disable interrupts in the isr so that they remain disabled after the isr returns, the individual interrupt enable bits for each source of interrupts must be cleared. 3.7.3 interrupt latency the interrupt latency is the time from the interrupt event occurring to rst isr instruction being latched from the decode to the execute stage (see section 4.3). if the interrupt comes from a port b input and the sync bit in the fuse1 register is 0, an additional two core clock cycles of synchronization delay are added to the interrupt latency. the ireadi or iwritei instructions are blocking (i.e. prevent other instructions and interrupts from being ex ecuted) for 4 core clock cycles. the iread or iwrite instructions are blocking for 4 core clock cycles while operating on program ram, and non-blocking (single cycle) while operating on external memory. when an interrupt event is triggered, the cpu speed is changed to the speed speci ed by the intspd register (the spdreg register is copied to a shadow register, then loaded with the value from the intspd register). if intspd is set the same as spdreg when an interrupt occurs, then the interrupt latency is 3 core clock cycles for synchronous interrupts. if not, then the interrupt latency is 3 core clock cycles, plus the speed change (delay described in section 3.5). 3.7.4 return from interrupt the reti instruction word includes three bits which control its operation, as shown in table 3-5. the three bits are speci ed from assembly language in a literal (e.g. reti #0x7 to specify all bits as 1). updating the interrupt vector allows the programmer to implement a sequential state machine. the next interrupt will resume the code directly after the previous reti instruction. the reti instruction takes 1 cycle to execute, and there is a further delay of 2 cycles at the mainline code speed to load the pipeline before the mainline code is resumed. ta b le 3-4 gie bit handling event effect enter isr (interrupt) gie bit is cleared exit isr ( reti instruction) gie bit is set setb xcfg,7 instruction (inside isr) enable interrupts for nested interrupt support clrb xcfg,7 instruction (inside isr) nothing, the gie bit is already clear setb xcfg,7 instruction (mainline code) enable interrupts clrb xcfg,7 instruction (mainline code) disable interrupts ta b le 3-5 reti instruction options bit function 2 reinstate the pre-interrupt speed 1 = enable, 0 = disable 1 store the pc+1 value in the intvech and intvecl registers 1 = enable, 0 = disable 0 add w to the t0tmr register 1 = enable, 0 = disable
26 www.ubicom.com IP2012 / ip2022 data sheet note: if reti can return to flash program memory, insure that all flash reads or writes are complete (xcfg bit 0 = 0) before reti is executed. 3.7.5 disabled interrupt resources if a peripheral is disabled and its interrupt ag is cleared, the peripheral does not have the ability to set an interrupt ag. the interrupt ag, however, is still a valid source of interrupt (if software sets an interrupt ag, the corresponding interrupt enable bit is set, and the gie bit is set, then the cpu will be interrupted whether or not the peripheral is enabled or disabled). if a peripheral is disabled inside the isr, then its interrupt ag must be cleared to prevent an undesired interrupt from being taken when the isr completes or when gie is enabled (enabling nested interrupts - see section 3.7.2). 3.8 reset there are ve sources of reset: ?p ow er-on reset (por; reset occurs at power up) ? brown-out reset (bor) ?w atchdog reset ? external reset (from the rst pin) ?t ool reset (from the debugging interface) each of these reset conditions causes the program counter to branch to the reset vector at the top of the program memory (word address 0xfff0 or byte address 0x1ffe0). the IP2012 / ip2022 incorporates a power-on reset (por) detector that generates an internal reset as dvdd r ises during power-up. figure 3-12 is a block diagram of the reset logic. the startup timer controls the reset time- out delay. the reset latch controls the internal reset signal. on power-up, the reset latch is cleared (cpu held in reset), and the startup timer starts counting once it detects a valid logic high signal on the rst pin. once the startup timer reaches the end of the timeout period, the reset latch is cleared, releasing the cpu from reset. note: cpu operation does not start until the cpu is released from reset and valid core clocks are received past the system clock suspend circuit (see wudx block in figure 3-17). so, for a por with fuse0 register wudx=350us, for example, the core starts operation ~70ms after power up. for a por with wudx= 1.1sec, the core starts operation ~1.1sec after power up. the pspcfg (address 0x06e) register contains two bits to indicate possible sources of the reset, wd and bo. the wd bit is cleared on reset unless the reset was caused by the watchdog timer, in which case the wd bit is set. the bo bit is cleared on reset unless the reset was caused by the brown-out logic, in which case, the bo bit is set . figure 3-13 shows a power-up sequence in which rst is not tied to the dvdd pin and the dvdd signal is allowed to rise and stabilize before rst pin is brought high. the wudx2:0 bits of the fuse0 register specify the length of time from the rising edge of rst until the device leaves reset. figure 3-12 on-chip reset circuit block diagram start-up timer brown-out detection rst dvdd watchdog timer overflow watchdog rc clock (~14khz) time-out internal reset signal (active low) por power-on reset 515-023d.eps clear for rst, tool reset or watchdog = wudx2:0 (fuse0) for por or bor (1025 x 70us) 70ms avdd tool reset core clock core reset (active low, initially low) ff ff
IP2012 / ip2022 data sheet www.ubicom.com 27 figure 3-13 power-up, separate rst signal figure 3-14 shows the on-chip power-on reset sequence in which the rst and dvdd pins are tied together. the d vdd signal is stable before the startup timer expires. in this case, the cpu receives a reliable reset. figure 3-14 power-on reset, rst tied to dvdd however, figure 3-15 depicts a situation in which dvdd r ises too slowly. in this scenario, the startup timer will time out prior to dvdd reaching a valid operating voltage level (dvdd min). this means the cpu will come out of reset and start operating with the supply voltage below the level required for reliable performance. in this situation, an e xternal rc circuit is recommended for driving rst . the rc delay should exceed ve times the time period required for dvdd to reach a valid operating voltage. figure 3-15 dvdd rise time exceeds tstartup figure 3-16 shows the recommended external reset circuit. the external reset circuit is required only if the d vdd rise time has the possibility of being too slow (refer to svdd speci cation in section 8.4). figure 3-16 external reset circuit the diode d discharges the capacitor when dvdd is powered down. r1 = 100 ? to 1k ? will limit any current o wing into rst from external capacitor c1. this protects the rst pin from breakdown due to electrostatic discharge (esd) or electrical overstress (eos). r2 < 40k ? is recommended to make sure that voltage drop across r2 leaves the rst pin above a vih level. c1 should be chosen so that r2 c1 exceeds ve times the time period required for dvdd to reach a valid operating voltage. 515-019c.eps dvdd rst por wudx startup timer (time-out) internal reset signal dvdd rst por startup timer (time-out) internal reset signal 515-022e.eps 70ms dvdd rst por startup timer (time-out) internal reset signal 515-020e.eps 70ms dvdd c1 r2 r1 515-021a.eps rst ip2022
28 www.ubicom.com IP2012 / ip2022 data sheet 3.8.1 brown-out detector the on-chip brown-out detection circuitry resets the cpu when avdd dips below the brown-out voltage level programmed in the bor2:0 bits of the fuse1 register (refer to section 3.10.2). bits in the fuse1 register are flash memory cells which cannot be changed dynamically during program execution. the device is held in reset as long as avdd stays below the brown-out voltage. the cpu will come out of reset when avdd rises between 100mv and 200mv above the brown-out voltage (the cpu may never come out of brownout reset, even after avdd returns to acceptable level, if the brownout setting is too high). therefore, the 2.10v setting is recommended. the brown-out level can be programmed using the bor2:0 bits in the fuse1 register, as shown in section 3.10.2. 3.8.2 reset and interrupt vectors after reset, the pc is loaded with 0xfff0, which is near the top of the program memory space. typical activities for the reset initialization code include: ? setting up the fcfg register with appropriate values f or ash timing compensation. ? issuing a speed instruction to initialize the cpu core clock speed. ? checking for the cause of reset (brown-out voltage, w atchdog timer over ow , or other cause). in some ap- plications, a ?warm? reset allows some data initializa- tion procedures to be skipped. ? copying speed-critical sections of code from ash memory to program ram. ? setting up data memory structures (stacks, tables, etc.). ? initializing peripherals for operation (timers, etc.). ? initializing the dynamic interrupt vector and enabling interrupts. because the default interrupt vector location is 0, which is in program ram, interrupts should not be enabled until the isr is loaded in shadow ram or the dynamic interrupt v ector is loaded with the address of an isr in ash memory. there is a single dynamic interrupt vector shared by all interrupts. the interrupt vector can be changed by loading the intvech and intvecl registers, or by issuing a reti instruction with an option specifying that the interrupt vector should be updated with the current pc v alue plus 1. 3.8.3 register states following reset the effect of different reset sources on a register depends on the register and the type of reset operation. some registers are initialized to speci c values, some are left unchanged, and some are unde ned. a register that starts with an unknown value should be initialized by the software to a known value if it is going to be used (no need to initialize unused registers nor data memory). do not simply test the initial state and rely on it starting in that state consistently. see table 7-1 for more detailed information.
IP2012 / ip2022 data sheet www.ubicom.com 29 3.9 clock oscillator there are two clock oscillators, the osc oscillator and the r tclk oscillator. using the pll clock multiplier, the osc clock is intended to provide the time base for running the cpu core at speeds up to 120mhz for the standard v ersion, and at 160 mhz for the faster version. the rtclk oscillator operates at 32.768khz using an external crystal. this oscillator is intended for running the real-time timer when the osc oscillator and pll clock multiplier are turned off. either clock source can be driven by an e xternal clock signal up to 120mhz. figure 3-17 shows the clock logic for the ip2022, and figure 3-18 shows that of the IP2012. the pll clock m ultiplier has a x ed multiplication factor of 50. the pll is preceded by a divider capable of any integer divisor between 1 and 8, as controlled by the pin2:0 bits of the fuse0 register (refer to section 3.10.1). the pll is f ollowed by a second divider capable of any integer divisor between 1 and 4, as controlled by the pout1:0 bits of the fuse0 register. a third divider which only affects the clock to the cpu core is controlled by the speed change mechanism described in section 3.4. see section 3.10.1 f or a description of the fuse0 wudx2:0 and wudp2:0 bits. note: bits in the fuse0 register are flash memory cells which cannot be changed dynamically during program execution. figure 3-17 ip2022-120 and IP2012-120 clock logic 515-002h.eps timer 1 timer 0 cpu core 0?120mhz timer 2 rttmr serdes clock spdreg divider post- scaler pre- scaler rtclk driver rtclk1 rtclk2 50x pll clock multiplier osc driver osc1 osc2 system clock 0?120 mhz pll bypass external memory logic (ip2022 only) ip2022-120, IP2012-120: crystal 4.75?5 mhz ext. 0?120 mhz crystal 32.768 khz ext. 0?120 mhz 4.75?5 mhz fuse0 register (bits 11:9) fuse0 register (bits 13:12) 237.5?250 mhz speed instruction (spdreg bits 5:4) speed instruction (spdreg bits 3:0) 0?120 mhz rtcfg register, rtss bit sxmode register (clks1:0) adc wudx2:0 wudp2:0 wudx2:0 sxclk (re0 or rf4) fuse0 0 1 11 10 01 00 01 00 10 11
30 www.ubicom.com IP2012 / ip2022 data sheet figure 3-18 ip2022-160 clock logic 3.9.1 external connections figure 3-19 shows the connections for driving the osc and/or rtclk clock sources with an external signal. to drive the osc clock source, the external clock signal is driven on the osc1 pin and the osc2 pin is left open. the e xternal clock signal driven on the osc1 pin may be any frequency up to 120 mhz. to drive the rtclk clock source, the external clock signal is driven on the rtclk1 input and the rtclk2 output is left open. the external clock signal driven on the rtclk1 pin may be any frequency up to 120 mhz. figure 3-19 external clock inputs figure 3-20 shows the connections for attaching a crystal to the osc and/or rtclk oscillator. for the osc oscillator, a crystal is connected across the osc1 and osc2 pins. for the rtclk oscillator, a 32.768khz crystal is connected across the rtclk1 and rtclk2 pins. there is about 4pf of capacitance on each of osc1 and osc2 pins to dvss and about 10pf of capacitance on each of rtclk1 and rtclk2 pins to dvss. there is also an internal feedback resistor (no external feedback resistor needed). for the osc crystal, a parallel resonant crystal is recommended that has a maximum esr of 100 ohms and a load capacitance rating of 12pf (requires 24pf on each of osc1 and osc2 pins). for the optional r tclk crystal, a parallel resonant crystal is recommended that has a maximum esr of 50k ohms, and a load capacitance rating of 12.5pf (requires 25pf on each of rtclk1 and rtclk2 pins). the crystal manufacturer?s load capacitance rating (c l ) should be equal to (c 1 x c 2 )/(c 1 + c 2 ), where c 1 = capacitance on osc1 (4pf + stray board capacitance + added capacitance), and c 2 = capacitance on osc2 (4pf + stray board capacitance + added capacitance). the trace length between the osc pins and the crystal should be as short as possible, to avoid noise coupling. when rtclk1 is unused, it should be tied to gnd. 515-101.eps timer 1 timer 0 cpu core 0?120mhz, 160mhz timer 2 rttmr serdes clock spdreg divider post- scaler pre- scaler rtclk driver rtclk1 rtclk2 50x pll clock multiplier osc driver osc1 osc2 system clock 0?120, 160 mhz pll bypass external memory logic crystal 32.768 khz ext. 0?120 mhz 3.2 mhz or 4.75-5 mhz fuse0 register (bits 11:9) fuse0 register (bits 13:12) 160 mhz or 237.5-250 mhz speed instruction (spdreg bits 5:4) speed instruction (spdreg bits 3:0) 0?120 mhz rtcfg register, rtss bit sxmode register (clks1:0) adc wudx2:0 wudp2:0 wudx2:0 sxclk (re0 or rf4) fuse0 0 1 11 10 01 00 01 00 10 11 ip2022-160: crystal 4.75?5 mhz, 3.2 mhz ext. 0?120 mhz rtclk1 rtclk2 externally generated clock open 515-024a.eps IP2012/ip2022 osc1 osc2 externally generated clock open fuse0 bit 15=1 fuse0 bit 14=1
IP2012 / ip2022 data sheet www.ubicom.com 31 figure 3-20 crystal connection 3.10 con guration block the con guration block is a set of ash memory registers outside of both program memory and data memory. these registers are not readable or writable at run time. the fuse0, fuse1 registers hold settings that must be speci ed by system designers. the other con guration b lock registers are used by software tools. the con guration block is readable but not writable when code protection is enabled. table 3-6 lists the con guration block registers. 515-025c.eps crystal crystal IP2012/ip2022 osc1 osc2 xtal (fuse0 bit 15=0) rtclk1 rtclk2 rtclk (fuse0 bit 14=0) 20pf 20pf 15pf 15pf ta b le 3-6 con guration block word address words name description 0x00010000 1 fuse0 fuse0 register 0x00010001 1 fuse1 fuse1 register 0x00010002 to 0x00010003 2 - reserved 0x00010004 1 trim0 trim0 register, factory programmed to fbfe 0x00010005 to 0x0001001d 25 - reserved 0x0001001e- 0x0001001f 2 freq osc1 input frequency during device pro- gr amming - used by tools only 0x00010020 to 0x00010027 8 vcompany company name 0x00010028 to 0x0001002f 8 vproduct product name 0x00010030 to 0x00010031 2 vversion software version 0x00010032 to 0x00010033 2 vsoftdate software date 0x00010034 to 0x00010035 2 vprogdate programming date 0x00010036 to 0x0001003f 10 - reserved t otal 16-bit words 64
32 www.ubicom.com IP2012 / ip2022 data sheet 3.10.1 fuse0 register (not run-time programmable) 15 14 13 12 11 10 9876543210 xt al r tclk pout1:0 pin2:0 reserved wudp2:0 wudx2:0 figure 3-21 fuse0 register xt al osc2 crystal drive output 0 = enabled ? use for crystal clock 1 = disabled ? use for external clock r tclk r tclk2 crystal drive output 0 = enabled ? use for crystal clock 1 = disabled ? use for external clock pout1:0 speci es pll clock multiplier postscaler divisor 00 = 1 (reserved) 01 = 2 10 = 3 11 = 4 pin2:0 speci es pll clock multiplier prescaler divisor 000 = 1 100 = 5 001 = 2 101 = 6 010 = 3 110 = 7 011 = 4 111 = 8 wudp2:0 speci es system clock suspend time during pll startup (after a speed instruction clears the pll bit in the spdreg register). 000 = 140 s 100 = 1 ms 001 = 210 s 101 = 2 ms 010 = 350 s 110 = 5 ms 011 = 630 s 111 = 9 ms wudx2:0 speci es system clock suspend time during osc and rtclk start-up. used to keep the clock from prop- agating to the core before the crystal achieves valid signal levels (see figure 3-17). also keeps rst asserted except for por and bor. 000 = 450 s 001 = 1 ms 010 = 5 ms 011 = 9 ms 100 = 18 ms 101 = 72 ms 110 = 574 ms ? 1147 ms ? ?. clock suspend time after por is twice this long if the watchdog is enabled in fuse1 to a value less than wudx. 111 =
IP2012 / ip2022 data sheet www.ubicom.com 33 3.10.2 fuse1 register (not run-time programmable) 15 14 13 7 6 5 4 3 2 1 0 cp sync reserved bor2:0 wdte wdps2:0 figure 3-22 fuse1 register cp clear to enable code protection. once cleared, this bit cannot be set until the entire device is erased. when code protection is enabled, program memory reads as all 0 to an external device programmer. this bit does not affect access to program memory made by software, using the iread, ireadi, iwrite, iwritei, ferase, fwrite and fread instructions. in-system debugging is not av ailable when code protection is enabled. code protection does not protect the con guration block against reading, only against writing. note: after clearing this bit during programming, code protect is not activated until the part is powered down or reset. 0 = enabled disabled 1 = sync set to read directly from the port pins through the rxin register, clear to read through a cpu core clock synchronization register. this bit should be clear if any external devices that can be read from i/o port pins are running asynchronously to the cpu core clock. see figure 5-1. 0 = enabled disabled 1 = bor2:0 speci es brown-out voltage level. if avdd goes below this level, the IP2012 / ip2022 is reset. this set- ting should be at least 0.2v below the minimum operating avdd, because there is a maximum of 0.2v h ysteresis to leave brownout reset after power up and after brownout reset occurs. 000 = 2.30v 0.1v do not use unless avdd 2.50v 001 = 2.25v 0.1v do not use unless avdd 2.45v 010 = 2.20v 0.1v 011 = 2.15v 0.1v 100 = 2.10v 0.1v recommended 101 = reserved 110 = reserved 111 = disabled, no brown-out reset can occur. wdte enables watchdog timer in run mode. disabled in debug mode regardless of this bit. 0 = disabled enabled 1 = wdps2:0 speci es the watchdog timer prescaler divisor. this controls the time period before the watchdog timer expires. if the watchdog timer is enabled, software must clear the watchdog timer periodically within this time period to prevent a reset of the IP2012 / ip2022 from occurring. the cwdt instruction or any reset clears both the watchdog timer and its prescaler. care must be taken to ensure that this setting is not greater than the maximum crystal start-up time plus the time required to get to the rst cwdt instruction. 000 = 1 (~20 ms) = 256 x wrc 100 = 16 (~320 ms) 001 = 2 (~40 ms) 4 (~80 ms) 8 (~160 ms) 101 = 32 (~640 ms) 010 = 110 = 64 (~1280 ms) 011 = 111 = 128 (~2560 ms)
34 www.ubicom.com IP2012 / ip2022 data sheet 3.10.3 trim0 register f actory programmed to $fbfe for 120mhz versions, $fbfd for 160mhz versions operating at 160mhz. must leave at factory default for proper operation. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 squelt3:0 squelt5 fpert cmpt2:0 squelt4 vcot3 squelt7:6 vcot2:0 figure 3-23 trim0 register squelt7:0 serdes squelch trim bits fpert controls ash block pulse erase, both for self-programming ferase and for the ferase command from the isd/isp interface 0 = 20 ms, if osc1 frequency and fcfg register settings are optimal 1 = reserved - 10ms block erase (do not use) cmpt2:0 comparator offset trim bits vcot3:0 pll vco frequency trim bits 1110 = 4.75?5.0 mhz into pll 1101 = 3.2 mhz into pll
IP2012 / ip2022 data sheet www.ubicom.com 35 4.0 instruction set architecture the IP2012 / ip2022 implements a powerful load-store risc architecture with a rich set of arithmetic and logical operations, including signed and unsigned 8-bit 8-bit integer multiply with a 16-bit product. the cpu operates on data held in 128 special-purpose registers, 128 global registers, and 3840 bytes of data memory. the special-purpose registers are dedicated to control and status functions for the cpu and peripherals. the global registers and data memory may be used for any functions required by software, the only distinction among them being that the 128 global registers (addresses 0x080 to 0x0ff) can be accessed using a direct addressing mode. the remaining 3840 bytes of data memory (between addresses 0x100 and 0xfff) must be accessed using indirect or indirect-with-offset addressing modes. the iph/ipl register is the pointer for the indirect addressing mode, and the dph/dpl and sph/spl registers are the pointers for the indirect-with-offset addressing modes. 4.1 addressing modes a 9-bit eld within the instruction, called the ?fr? eld, speci es the addressing mode and the address (in the case of direct addressing) or the address offset (in the case of indirect-with-offset addressing), as shown in table 4-1. (see figure 3-7 for data ram map.) 4.1.1 pointer registers when an addition or increment instruction (i.e. add , inc , incsz , or incsnz ) on the low byte of a pointer register (i.e. ipl, dpl, spl, or addrl) generates a carry, the high part of the register is incremented. for example, if the ip register holds 0x00ff and an inc ipl instruction is ex ecuted, the register will hold 0x0100 after the instruction. when a subtraction or decrement instruction (i.e. sub , subc , dec , decsz , or decsnz ) generates a borrow, the high part of the register is decremented. note: because carry and borrow are automatically handled, the addc and subc instructions are not needed f or arithmetic operations on pointer registers. ta b le 4-1 addressing mode summary ?fr? field mode syntax effective address (ea) restrictions 0 0000 0000 indirect mov w,(ip) mov (ip),w iph || ipl 0x020 < ea < 0xfff 0 0nnn nnnn direct, special- purpose registers mov w,fr mov fr,w nnnnnnn 0x002 < ea < 0x07f 0 1nnn nnnn direct, global registers mov w,fr mov fr,w 0x080 + nnnnnnn 0x080 < ea < 0x0ff 1 0nnn nnnn indirect with offset, data pointer mov w,offset(dp) mov offset(dp),w dph || dpl + nnnnnnn 0x000 < nnnnnnn < 0x07f 0x020 < ea < 0xfff 1 1nnn nnnn indirect with offset, stack pointer mov w,offset(sp) mov offset(sp),w sph || spl + nnnnnnn 0x000 < nnnnnnn < 0x07f 0x020 < ea < 0xfff
36 www.ubicom.com IP2012 / ip2022 data sheet 4.1.2 direct addressing mode figure 4-1 shows the direct addressing mode used to reference the special-purpose registers. seven bits from the ?fr? eld allow addressing up to 128 special-purpose registers. (not all 128 locations in this space are implemented in the IP2012 / ip2022; several locations are reserved for future expansion.) figure 4-1 direct mode, special-purpose registers the following code example uses direct mode. figure 4-2 shows the direct addressing mode used to reference the global registers. this mode is distinguished from the mode used to access the special-purpose registers with bit 7 of the ?fr? eld. because these registers have this additional addressing mode not available for the other data memory locations, they are especially useful f or holding global variables and frequently accessed data. figure 4-2 direct mode, global registers note: addresses from 0x000 to 0x01f can only be accessed with direct mode. 4.1.3 indirect addressing mode the indirect addressing mode is used when all of the bits in the ?fr? eld are clear. the location of the operand is speci ed by a 12-bit pointer in the iph and ipl registers. the upper four bits of the iph register are not used. figure 4-3 shows indirect mode. figure 4-3 indirect mode the following code example uses indirect mode. mov w,0x0012 ;load w with the contents of ;the memory location at 0x0012 ;(the datal register) 515-007a.eps 127 special-purpose registers 70 9-bit "fr" field from instruction 0 8 0nnnnnnn 0 76 515-008a.eps 127 global registers 70 9-bit "fr" field from instruction 0 8 1nnnnnnn 0 76 mov w,#0x03 ;load w with 0x03 mov iph,w ;load the high byte of the ;indirect pointer from w mov w,#0x85 ;load w with 0x85 mov ipl,w ;load the low byte of the ;indirect pointer from w mov w,(ip) ;load w with the contents of ;the memory location at ;effective address 0x0385 515-009a.eps 127 special-purpose registers 3840 bytes data memory iph register ipl register 70 n 0 n 7 nnnnnnn x 3 4 7 xxxn n n 0 9-bit "fr" field from instruction 0 8 00000000 0 128 global registers
IP2012 / ip2022 data sheet www.ubicom.com 37 4.1.4 indirect-with-offset addressing mode the indirect-with-offset addressing mode is used when bit 8 of the ?fr? eld is set. the location of the operand is speci ed by a 7-bit unsigned immediate from the ?fr? eld added to a 12-bit base address in a pointer register. when bit 7 of the ?fr? eld is clear, the dph/dpl register is selected as the pointer register. this register is accessed using the loadh and loadl instructions, which load its high and low bytes, respectively. the upper f our bits of the dph register are not used. figure 4-4 shows indirect-with-offset addressing using the dph/dpl register as the pointer register. figure 4-4 indirect-with-offset mode, data pointer the following code example uses indirect-with-offset addressing mode. when bit 7 of the ?fr? eld is set, the sph/spl register is selected as the pointer register. the upper four bits of the sph register are not used. figure 4-5 shows indirect-with- offset mode using the sph/spl register. in addition to this indirect-with-offset addressing mode, there are also push and pop instructions which automatically increment and decrement the sph/spl register while performing a data transfer between the top of stack and a data memory location speci ed by the ?fr? eld. stacks gr ow down from higher addresses to lower addresses. this stack addressing mechanism is completely independent from the hardware stack used for subroutine call and return. when a pop instruction is used with the indirect-with- offset addressing mode, the address calculation for the ?fr? operand is made using the value in the sph/spl register before the automatic increment, even though the stack operand itself is addressed using the value after the automatic increment. figure 4-5 indirect-with-offset mode, stack pointer mystuff= 0x038d ;define address mystuff loadh mystuff ;load the high byte of the ;dph/dpl pointer register ;with 0x03 loadl mystuff ;load the low byte of the ;dph/dpl pointer register ;with 0x8d 515-026a.eps 127 special-purpose registers dph register dpl register 70 n 0 n 7 nnnnnnn x 3 4 7 xxxn n n 0 9-bit "fr" field from instruction 1 8 0mmmmmmm 0 + 7 6 3840 bytes data memory 128 global registers mov w,8(dp) ;load w with the contents of ;the memory location at ;effective address 0x038d ;(i.e. 0x0385 + 0x0008) 515-027a.eps 127 special-purpose registers sph register spl register 70 n 0 n 7 nnnnnnn x 3 4 7 xxxn n n 0 9-bit "fr" field from instruction 1 8 1mmmmmmm 0 + 7 6 3840 bytes data memory 128 global registers
38 www.ubicom.com IP2012 / ip2022 data sheet 4.2 instruction set the instruction set consists entirely of single-word (16-bit) instructions, most of which can be executed at a rate of one instruction per clock cycle, for a throughput of up to 120 mips when executing out of program ram. assemblers may implement additional instruction mnemonics for the convenience of programmers, such as a long jump instruction which compiles to multiple IP2012 / ip2022 instructions for handling the page structure of program memory. refer to the assembler documentation f or more information about any instruction mnemonics implemented in the assembler. 4.2.1 instruction formats there are ve instruction formats: ?t w o-operand arithmetic and logical instructions ? immediate-operand arithmetic and logical instruc- tions ?j umps and subroutine calls ? bit operations ? miscellaneous instructions figure 4-6 shows the two-operand instruction format. the two-operand instructions perform an arithmetic or logical operation between the w register and a data memory location speci ed by the ?fr? eld. the d bit indicates the destination operand. when the d bit is clear, the destination operand is the w register. when the d bit is set, the destination operand is speci ed by the ?fr? eld. there are some exceptions to this behavior. the multiply instructions always load the 16-bit product into the mulh and w registers. the mulh register receives the upper 8 bits, and the w register receives the lower 8 bits. tr aditionally single-operand instructions, such as increment, are available in two forms distinguished by the d bit. when the d bit is clear, the source operand is speci ed by the ?fr? eld and the destination operand is the w register. when the d bit is set, the data memory location speci ed by the ?fr? eld is both the source and destination operand. also, there are a few cases of unrelated instructions, such as clr and cmp , which are distinguished by the d bit. figure 4-7 shows the immediate operand instruction fo r mat. in this format, an 8-bit literal value is encoded in the instruction eld. usually the w register is the destination operand, however this format also includes instructions that use the top of the stack or a special- purpose register as the destination operand. figure 4-8 shows the format of the jump and subroutine call instructions. 13 bits of the entry point address are encoded in the instruction. the remaining three bits come from the pa2:0 bits of the status register. figure 4-9 shows the format of the instructions that clear, set, and test individual bits within registers. the register is speci ed by the ?fr? eld, and a 3-bit eld in the instruction selects one of the eight bits in the register. figure 4-10 shows the format of the remaining instructions. 4.2.2 instruction types the instructions are grouped into the following functional categories: ? logical instructions ?a r ithmetic and shift instructions ? bit operation instructions ? data movement instructions ? program control instructions ? system control instructions logical instructions each logic instruction performs a standard logical operation (and, or, exclusive or, or logical complement) on the respective bits of the 8-bit operands. the result of the logic operation is written to w or to the data memory location speci ed by the ?fr? eld. all of these instructions take one clock cycle for execution. arithmetic and shift instructions each arithmetic or shift instruction performs an operation such as add, subtract, add with carry, subtract with carry, 15 10 9 8 0 opcode d ?fr? field figure 4-6 two-operand instruction format 15 8 7 0 opcode 8-bit literal (?#lit8?) figure 4-7 immediate-operand instruction format 15 13 12 0 opcode entry point address (?addr13?) figure 4-8 jump and call instruction format 15 12 11 9 8 0 opcode bit ?fr? field figure 4-9 bit operation instruction format 15 14 13 12 11 10 9 8 0 0000000 opcode figure 4-10 miscellaneous instruction format
IP2012 / ip2022 data sheet www.ubicom.com 39 rotate left or right through carry, increment, decrement, clear to zero, or swap high/low nibbles. the compare ( cmp ) instruction performs the same operation as subtract, but it only updates the c, dc, and z ags of the status register; the result of the subtraction is discarded. there are instructions available ( incsz , decsz ) that increment or decrement a register and simultaneously test the result. if the 8-bit result is zero, the next instruction in the program is skipped. these instructions can be used to make program loops. there are also compare-and-skip instructions ( cse , csne ) which perform the same operation as subtract, but perform a conditional skip without affecting either operand or the condition ags in the status register. all of the arithmetic and shift instructions take one clock cycle for execution, except in the case of the test-and-skip instructions when the tested condition is true and a skip occurs, in which case the instruction takes at least two cycles. if a skip instruction is immediately followed by a loadh , loadl , or page instruction (and the tested condition is true) then two instructions are skipped and the operation consumes three cycles. this is useful for skipping over a conditional branch to another page, in which a page instruction precedes a jmp instruction. if several page or loadh / loadl instructions immediately f ollow a skip instruction, then they are all skipped plus the next instruction and a cycle is consumed for each. these ?extended skip instructions? are interruptible, so they do not affect interrupt latency. bit operation instructions there are four bit operation instructions: ? setb ?sets a single bit in a data register without af- f ecting other bits ? clrb ?clears a single bit in a data register without af- f ecting other bits ? sb ?tests a single bit in a data register and skips the next instruction if the bit is set ? snb ?tests a single bit in a data register and skips the next instruction if the bit is clear all of the bit operation instructions take one clock cycle for ex ecution, except for test-and-skip instructions when the tested condition is true and a skip occurs. data movement instructions a data movement instruction moves a byte of data from a data memory location to either the w register or the top of stack, or it moves the byte from either the w register or the top of stack to a data memory location. the location is speci ed by the ?fr? eld. the sph/spl register pair points to the top of stack. this stack is independent of the hardware stack used for subroutine call and return. program control instructions a program control instruction alters the ow of the program by changing the contents of the program counter. included in this category are the jump, call, return-from- subroutine, and interrupt instructions. the jmp instruction has a single operand that speci es the entry point at which to continue execution. the entry point is typically speci ed in assembly language with a label, as in the following code example: if the carry bit is set to 1, the jmp instruction is executed and program execution continues where the do_carry label appears in the program. the call instruction works in a similar manner, except that it saves the contents of the program counter to the callh/calll registers before jumping to the new address. it calls a subroutine that is terminated by a ret , retw , or retnp instruction, as shown in the following code example: returning from a subroutine restores the saved program counter contents from the callh/calll registers, which causes program to resume execution with the instruction immediately following the call instruction (a nop instruction, in the above example) a program memory address contains 16 bits. the jmp and call instructions specify only the lowest thirteen bits of the jump/call address. the upper 3 bits come from the p a2:0 bits of the status register. an indirect relative jump can be accomplished by adding the contents of the w register to the pcl register (i.e. an add pcl,w instruction). program control instructions such as jmp , call , and ret alter the normal program sequence. when one of snb status,0 ;test the carry bit jmp do_carry ;jump to do_carry routine ;if c = 1 ... do_carry: ;jump destination label ... ;execution continues here call add_2bytes ;call subroutine ;add_2bytes nop ;execution returns to ;here after the ;subroutine is finished ... add_2bytes: ;subroutine label ... ;subroutine code goes ;here ret ;return from subroutine
40 www.ubicom.com IP2012 / ip2022 data sheet these instructions is executed, the execution pipeline is automatically cleared of pending instructions and re lled with new instructions, starting at the new program address. because the pipeline must be cleared, three clock cycles are required for execution, one to execute the instruction and two to reload the pipeline. system control instructions a system control instruction performs a special-purpose operation that sets the operating mode of the device or reads data from the program memory. included in this category are the following types of instructions: ? speed ?changes the cpu core speed (for saving power) ? break ?enters debug mode ? page ?writes to the pa2:0 bits in the status regis- ter ? loadh / loadl ?loads a 16-bit pointer into the dph and dpl registers ? iread ?reads a word from external memory, pro- gr am ash memory, or program ram ? ireadi ?reads a word (and auto-increments addr by 2) from program ash memory, or program ram ? iwrite ?writes a word to external memory or pro- gr am ram ? iwritei ?writes a word (and auto-increments addr by 2) to program ram ? fread ?reads a word from ash program memory ? fwrite ?writes a word to ash program memory ? ferase ?erases a block of ash program memory ? cwdt ?clears the watchdog timer 4.3 instruction pipeline an instruction goes through a four-stage pipeline to be ex ecuted, as shown in figure 4-11. the rst instruction is f etched from the program memory on the rst core clock cycle. on the second clock cycle, the rst instruction is decoded and a second instruction is fetched. on the third clock cycle, the rst instruction is executed, the second instruction is decoded, and a third instruction is fetched. on the fourth clock cycle, the rst instruction?s results are written to its destination, the second instruction is ex ecuted, the third instruction is decoded, and a fourth instruction is fetched. once the pipeline is full, instructions are executed at the rate of one per clock cycle. instructions that directly affect the contents of the program counter (such as jumps and calls) require that the pipeline be cleared and subsequently re lled. therefore, these instructions take two additional clock cycles (the pc will be changed during the execute cycle of a jump instruction). stage core cycle 1 core cycle 2 core cycle 3 core cycle 4 f etch instruction 1 instruction 2 instruction 3 instruction 4 decode instruction 1 instruction 2 instruction 3 execute instruction 1 instruction 2 write instruction 1 figure 4-11 pipeline execution
IP2012 / ip2022 data sheet www.ubicom.com 41 4.4 subroutine call/return stack a 16-level hardware call/return stack is provided for saving the program counter on a subroutine call and restoring the program counter on subroutine return. the stack is not mapped into the data memory address space e xcept for the top level, which is accessible as the callh and calll registers. software can read and write these registers to implement a deeper stack, in those cases which require nesting subroutines more than 16 levels deep. this stack is completely independent of the stack used with the push and pop instructions and the sph/spl register pair. note: the calll and callh registers require special attention as modi cation of these values (the top of the stack) changes the return vector. when a subroutine is called, the return address is pushed onto the subroutine stack, as shown in figure 4-12. speci cally, each saved address in the stack is moved to the next lower level to make room for the new address to be saved. stack 1 receives the contents of the program counter. stack 16 is overwritten with what was in stack 15. the contents of stack 16 are lost. figure 4-12 stack operation on subroutine call when a return instruction is executed the subroutine stack is popped, as shown in figure 4-13. speci cally, the contents of stack 1 are copied into the program counter and the contents of each stack level are moved to the next higher level. when a value is popped off the stack, the bottom entry is initialized to 0xffff. for example, stack 1 receives the contents of stack 2, etc., and stack 15 is ov erwritten with the contents of stack 16. stack 16 is initialized to 0xffff. figure 4-13 stack operation on subroutine return f or program bugs involving stack under ow, the instruction at byte address 0x1fffe (word address 0xffff) can be used to jump to an appropriate handler. f or example, system recovery may be possible by jumping to the reset vector at byte address 0x1ffe0 (word address 0xfff0). the options for returning from a call are: 1. ret - the stack will be popped (callh/l will be load- ed into pch/l) and the page bits (pa2:0 in the sta- tus register) will be loaded with the upper 3 bits of callh. 2. retnp - same as above, but pa2:0 are not changed. 3. retw #lit - same as ret, but also moves literal to w. 515-010a.eps stack 1 stack 2 program counter (15:0) stack 16 contents are discarded stack 3 stack 4 stack 5 stack 6 stack 7 stack 8 stack 9 stack 10 stack 11 stack 12 stack 13 stack 14 stack 15 stack 16 callh/calll

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42 www.ubicom.com IP2012 / ip2022 data sheet 4.5 key to abbreviations and symbols 4.6 instruction set summary tables ta b le 4-2 through table 4-7 list all of the IP2012 / ip2022 instructions, organized by category. for each instruction, the table shows the instruction mnemonic (as written in assembly language), a brief description of what the instruction does, the number of instruction cycles required f or execution, the binary opcode, and the ags in the status register affected by the instruction. although the number of clock cycles for execution is typically 1, for the skip instructions the exact number of cycles depends whether the skip is taken or not taken. t aking the skip adds 1 cycle. the effect of extended skip instructions (i.e. a skip followed by a loadh , loadl , or page instruction) is not shown. f or more detailed description, refer to the programmer?s reference manual. symbol description addr13 13-bit address in assembly language instruc- tion addr16 16-bit address in assembly language instruc- tion bit bit position selector bit in opcode bo brown-out bit in the pspcfg register (bit 0) c carry bit in the status register (bit 0) dc digit carry bit in the status register (bit 1) dph upper half of data pointer for indirect-with-off- set addressing (global le register 0x00c) dpl lower half of data pointer for indirect-with-off- set addressing (global le register 0x00d) f file register address bit in opcode fr file register eld (a 9-bit le register address speci ed in the instruction) iph indirect pointer high - upper half of pointer for indirect addressing (global le register 0x004) ipl indirect pointer low - lower half of pointer for indirect addressing (global le register 0x005) k constant value bit in opcode n numerical value bit in opcode p a2:pa0 p age bits in the status register (bits 7:5) pcl virtual register for direct pc modi cation (glo- bal le register 0x009) sph upper half of stack pointer for indirect-with-off- set addressing (global le register 0x006) spl lower half of stack pointer for indirect-with-off- set addressing (global le register 0x007) status status register (global le register 0x00b) w wo r king register wd w atchdog timeout bit in the pspcfg register (bit 1) wdt w atchdog timer counter and prescaler z zero bit in the status register (bit 2 , file register/bit selector separator (e.g. clrb status,z ) != inequality # immediate literal designator in assembly lan- guage instruction (e.g. mov w,#0xff ) #lit8 8-bit literal value in assembly language instruction & logical and (address) contents of memory referenced by address ^ logical exclusive or | logical or || concatenation symbol description
IP2012 / ip2022 data sheet www.ubicom.com 43 ta b le 4-2 logical instructions assembler syntax pseudocode definition description core cycles opcode flags affected and fr,w fr = fr & w and fr,w into fr 1 0001 011f ffff ffff z and w,fr w = w & fr and w,fr into w 1 0001 010f ffff ffff z and w,#lit8 w = w & lit8 and w,literal into w 1 0111 1110 kkkk kkkk z not fr fr = fr complement fr into fr 1 0010 011f ffff ffff z not w,fr w = fr complement fr into w 1 0010 010f ffff ffff z or fr,w fr = fr | w or fr,w into fr 1 0001 001f ffff ffff z or w,fr w = w | fr or w,fr into w 1 0001 000f ffff ffff z or w,#lit8 w = w | lit8 or w,literal into w 1 0111 1101 kkkk kkkk z xor fr,w fr = fr ^ w xor fr,w into fr 1 0001 101f ffff ffff z xor w,fr w = w ^ fr xor w,fr into w 1 0001 100f ffff ffff z xor w,#lit8 w = w ^ lit8 xor w,literal into w 1 0111 1111 kkkk kkkk z ta b le 4-3 arithmetic and shift instructions assembler syntax pseudocode definition description core cycles opcode flags affected add fr,w fr = fr + w add fr,w into fr 1 0001 111f ffff ffff c, dc, z add w,fr w = w + fr add w,fr into w 1 0001 110f ffff ffff c, dc, z add w,#lit8 w = w + lit8 add w,literal into w 1 0111 1011 kkkk kkkk c, dc, z addc fr,w fr = c + fr + w add carry,fr,w into fr 1 0101 111f ffff ffff c, dc, z addc w,fr w = c + w + fr add carry,w,fr into w 1 0101 110f ffff ffff c, dc, z clr fr fr = 0 clear fr 1 0000 011f ffff ffff z cmp w,fr fr - w compare w,fr then update status 1 0000 010f ffff ffff c, dc, z cmp w,#lit8 lit8 - w compare w,literal then update status 1 0111 1001 kkkk kkkk c, dc, z cse w,fr if (fr - w) = 0 then skip compare w,fr then skip if equal 1 or 2 (skip) 0100 001f ffff ffff none cse w,#lit8 if (lit8 - w) = 0 then skip compare w,literal then skip if equal 1 or 2 (skip) 0111 0111 kkkk kkkk none csne w,fr if (fr - w) != 0 then skip compare w,fr then skip if not equal 1 or 2 (skip) 0100 000f ffff ffff none csne w,#lit8 if (lit8 - w) != 0 then skip compare w,literal then skip if not equal 1 or 2 (skip) 0111 0110 kkkk kkkk none cwdt wdt = 0 clear watchdog timer 1 0000 0000 0000 0100 none dec fr fr = fr - 1 decrement fr into fr 1 0000 111f ffff ffff z dec w,fr w = fr -1 decrement fr into w 1 0000 110f ffff ffff z decsnz fr fr = fr - 1 if fr != 0 then skip decrement fr into fr then skip if not zero (status not updated) 1 or 2 (skip) 0100 111f ffff ffff none
44 www.ubicom.com IP2012 / ip2022 data sheet decsnz w,fr w = fr - 1 if fr != 0 then skip decrement fr into w then skip if not zero (status not updated) 1 or 2 (skip) 0100 110f ffff ffff none decsz fr fr = fr - 1 if fr = 0 then skip decrement fr into fr then skip if z ero (status not updated) 1 or 2 (skip) 0010 111f ffff ffff none decsz w,fr w = fr - 1 if fr = 0 then skip decrement fr into w then skip if z ero (status not updated) 1 or 2 (skip) 0010 110f ffff ffff none inc fr fr = fr + 1 increment fr into fr 1 0010 101f ffff ffff z inc w,fr w = fr + 1 increment fr into w 1 0010 100f ffff ffff z incsnz fr fr = fr + 1 if fr != 0 then skip increment fr into fr then skip if not zero (status not updated) 1 or 2 (skip) 0101 101f ffff ffff none incsnz w,fr w = fr + 1 if fr != 0 then skip increment fr into w then skip if not zero (status not updated) 1 or 2 (skip) 0101 100f ffff ffff none incsz fr fr = fr + 1 if fr = 0 then skip increment fr into fr then skip if z ero (status not updated) 1 or 2 (skip) 0011 111f ffff ffff none incsz w,fr w = fr + 1 if fr = 0 then skip increment fr into w then skip if z ero (status not updated) 1 or 2 (skip) 0011 110f ffff ffff none muls w,fr mulh || w = w fr signed 8 8 multiply (bit 7 = sign); w x fr into mulh || w (bit 7 of mulh is result sign) 1 0101 010f ffff ffff none muls w,#lit8 mulh || w = w lit8 signed 8 8 multiply (bit 7 = sign); w x literal into mulh || w (bit 7 of mulh is result sign) 1 0111 0011 kkkk kkkk none mulu w,fr mulh || w = w fr unsigned 8 8 multiply; w x fr into mulh || w 1 0101 000f ffff ffff none mulu w,#lit8 mulh || w = w lit8 unsigned 8 8 multiply; w x lit- eral into mulh || w 1 0111 0010 kkkk kkkk none rl fr fr || c = c || fr rotate fr left through carry into fr 1 0011 011f ffff ffff c rl w,fr w || c = c || fr rotate fr left through carry into w 1 0011 010f ffff ffff c rr fr c || fr = fr || c rotate fr right through carry into fr 1 0011 001f ffff ffff c rr w,fr c || w = fr || c rotate fr right through carry into w 1 0011 000f ffff ffff c sub fr,w fr = fr - w subtract w from fr into fr 1 0000 101f ffff ffff c, dc, z sub w,fr w = fr - w subtract w from fr into w 1 0000 100f ffff ffff c, dc, z sub w,#lit8 w = lit8 - w subtract w from literal into w 1 0111 1010 kkkk kkkk c, dc, z subc fr,w fr = fr - c - w subtract carr y ,w from fr into fr 1 0100 101f ffff ffff c, dc, z subc w,fr w = fr - c - w subtract carr y , w from fr into w 1 0100 100f ffff ffff c, dc, z ta b le 4-3 arithmetic and shift instructions (continued) assembler syntax pseudocode definition description core cycles opcode flags affected
IP2012 / ip2022 data sheet www.ubicom.com 45 swap fr fr = fr3:0 || fr7:4 swap high,low nibbles of fr into fr 1 0011 101f ffff ffff none swap w,fr w = fr3:0 || fr7:4 swap high,low nibbles of fr into w 1 0011 100f ffff ffff none test fr if fr = 0 then z = 1 else z = 0 t est fr for zero and update z 1 0010 001f ffff ffff z ta b le 4-3 arithmetic and shift instructions (continued) assembler syntax pseudocode definition description core cycles opcode flags affected ta b le 4-4 bit operation instructions assembler syntax pseudocode definition description core cycles opcode flags affected clrb fr,bit fr,bit = 0 clear bit in fr 1 1000 bbbf ffff ffff none sb fr,bit if fr,bit = 1 then skip test bit in fr then skip if set 1 or 2 (skip) 1011 bbbf ffff ffff none setb fr,bit fr,bit = 1 set bit in fr 1 1001 bbbf ffff ffff none snb fr,bit if fr,bit = 0 then skip test bit in fr then skip if clear 1 or 2 (skip) 1010 bbbf ffff ffff none ta b le 4-5 data movement instructions assembler syntax pseudocode definition description core cycles opcode flags affected mov fr,w fr = w move w into fr 1 0000 001f ffff ffff none mov w,fr w = fr move fr into w 1 0010 000f ffff ffff z mov w,#lit8 w = lit8 move literal into w 1 0111 1100 kkkk kkkk none push fr (sp) = fr, then sp = sp - 1 move fr onto top of stack 1 0100 010f ffff ffff none push #lit8 (sp) = lit8, then sp = sp - 1 move literal onto top of stack 1 0111 0100 kkkk kkkk none pop fr fr = (sp + 1), then sp = sp + 1 move top of stack + 1 into fr 1 0100 011f ffff ffff none
46 www.ubicom.com IP2012 / ip2022 data sheet ta b le 4-6 program control instructions assembler syntax description core cycles opcode flags affected call addr13 call subroutine 3 110k kkkk kkkk kkkk none jmp addr13 j ump 3 111k kkkk kkkk kkkk none int software interrupt 3 0000 0000 0000 0110 none nop no operation 1 0000 0000 0000 0000 none ret return from subroutine 3 0000 0000 0000 0111 p a2:0 retnp return from subroutine, without updating page bits 3 0000 0000 0000 0010 none reti #lit3 return from interrupt (see section 3.7.4) 3 0000 0000 0000 1nnn all retw #lit8 return from subroutine with literal into w 3 0111 1000 kkkk kkkk p a2:0 ta b le 4-7 system control instructions assembler syntax description core cycles opcode flags affected break software breakpoint. keeps pc from advancing and stops timers, including the w atchdog timer 1 0000 0000 0000 0001 none breakx software breakpoint, extending the skip 1 0000 0000 0000 0101 none ferase erase a 256 word ash block 1 ? 0000 0000 0000 0011 none fread read flash memory 1 ? 0000 0000 0001 1011 none fwrite write flash memory 1 ? 0000 0000 0001 1010 none iread read external/program memory 4(blocking), 1 ? (nonblocking) 0000 0000 0001 1001 none ireadi read program memory and increment addrl to next even addrl 4(blocking), 1 ? (nonblocking) 0000 0000 0001 1101 none iwrite write into external memory/program ram 4(blocking), 1 ? (nonblocking) 0000 0000 0001 1000 none iwritei write into program ram and increment addrl to next even addrl 4(blocking), 1 ? (nonblocking) 0000 0000 0001 1100 none loadh addr8 load high data address into dph 1 0111 0000 kkkk kkkk none loadl addr8 load low data address into dpl 1 0111 0001 kkkk kkkk none page addr3 load page bits from program address into p a2:0 of the status register 1 0000 0000 0001 0nnn p a2:0 speed #lit8 change cpu speed by writing into the spdreg register 1 0000 0001 nnnn nnnn none ?. only occupies the cpu pipeline for 1 cycle, but the operation is not complete until xcfg:0 = 0. (refer to sec- tion 4.7)
IP2012 / ip2022 data sheet www.ubicom.com 47 4.7 program memory self-programming and read instructions the IP2012 / ip2022 has several instructions used to read and write the program ram and the program ash memory. these instructions allow the program ash memory to be read and written through special-purpose registers in the data memory space, which allows the ash memory to be used to store both program code and data. because no special programming voltage is required to write to the ash memory, any application may take advantage of this feature at run-time. typical uses include saving phone numbers and passwords, downloading new or updated software, and logging infrequent events such as errors and watchdog timer over ow. the self-programming instructions are not affected by the code-protection ag (the cp bit of the fuse1 register), so the entire program memory is readable and writable by any software running on the IP2012 / ip2022. note: it is highly recommended to enable the brown-out reset feature if self-programming instructions are being used in user program code (see section 3.8.1 for more information about bor). this will avoid corruption of ash memory during power down. there are seven instructions used for self-programming, as shown in table 4-8. certain uses of the instructions are not valid. in these cases, the instruction is executed as though it were a nop instruction (i.e. the program counter is incremented, but no other registers or bits are affected). blocking instructions take 4 cycles to complete, and prevent other instructions from executing. non-blocking instructions occupy the cpu pipeline for only one cycle, b ut they launch a multi-cycle operation which is not complete until indicated by the fbusy bit in the xcfg register becoming clear. the datah/datal register is a 16-bit data buffer used for loading or unloading data in program memory. the addrx/addrh/addrl register holds a 24-bit byte address used to specify the low-byte of the desired word location in program memory. like the other pointer registers (iph/ipl, dph/dpl, and sph/spl), addition to the low byte of the register that results in carry will cause the high part of the register (addrx/addrh) to be incremented. subtraction from the low byte of the register that results in borrow will cause the high part of the register to be decremented. note: if addrsel is modi ed in the isr, it must rst be shadowed in software, and restored before reti . note: addrl bit 0 is ignored as the a0 address bit is handled automatically in hardware. software should use the fbusy bit to check that a previous ash write or erase operation has completed before executing another instruction that accesses ash memory, before jumping to or calling program code in ash memory, and before changing the cpu core speed. it is not necessary to check the fbusy bit if enough cycles are allowed for the ash operation to complete. see description of frdts1:0, frdtc1:0 and fwrt3:0 in section 7.1.5 for more details. software must not attempt to execute out of ash memory while the fbusy bit is set, because the ash memory is unreadable during that time. therefore, code which reads, writes, or erases ash memory, using the fread , fwrite or ferase instructions, must execute from program ram. software m ust provide at least four cycles between an fread and ta b le 4-8 instructions used for self-programming operation program ram (addrx = 00) flash (addrx =01) external memory (addrx = 80 or 81) read iread (blocking) ireadi (blocking) fread (nonblocking) 1 iread 2 ireadi 2 iread (nonblocking) write iwrite (blocking) iwritei (blocking) fwrite (nonblocking) 3 iwrite (nonblocking) erase n/a ferase (nonblocking) 3 n/a 1 ? rules 1, 2, 3, 5, 7, and 10 below apply. 2 ? rules 2, 3, 5, 7, and 10 below apply. if executed from program ram, the instruction is nonblocking; if executed from flash, it is blocking. 3 ? rules 1, 2, and 4?10 below apply.
48 www.ubicom.com IP2012 / ip2022 data sheet reading datah/datal, or ensure that the minimum ash read time is met. unlike ram, ash memory requires an explicit erase operation before being written. the ferase instruction is used to erase a 512-byte (256-word) block of ash memory (it brings all bits to 1, see table 4-9). after the b lock has been erased, individual words can be written with the fwrite instruction ( fwrite will not change a 0 to 1). for example, an ferase instruction executed on any byte address from 0x10000 to 0x100fe erases the whole block spanning those addresses. the self- programming instructions have no access to the ash memory bits in the con guration block. rules/troubleshooting for fread / fwrite / ferase and iread / ireadi of ash: 1. must be executing out of program ram, with addrx = 01. 2. fcfg register must be correctly con gured (refer to section 7.1.5). 3. for an fread or iread / ireadi of ash, there m ust be at least 3 core cycles between the read in- struction and a read of datah or datal, or the mini- m um ash read time must be met. 4. no speed commands while fread , fwrite or fe- rase are busy (while xcfg bit 0 = 1). 5. do not jump to ash memory while executing fread / fwrite / ferase . if intvec is in ash, en- sure interrupts are disabled. 6. fwrite will not change a 0 to a 1 (use ferase rst). 7. xcfg bit 0 = 0 before execution (even during isr) or suf cient time is allowed to complete previous opera- tions on ash. 8. xcfg bit 6 = 1, otherwise fwrite and ferase be- have as nop . 9. make sure interrupts are disabled or that the intspd v alue matches the spdreg value. for iread or ireadi of ash from ash, a more practical solution is to jump to a routine in program ram. 10. wait 1 cycle after changing addrx bit 7, emcfg bit 7, or addrsel before executing an fread , fwrite , ferase , iread , ireadi , iwrite , or iwritei instruction. 11. do not write to datah at the same time an iread of external memory is causing a write of datal. 4.7.1 flash timing control the fcfg register controls the timing of ash memory operations. see section 7.1.5 for a description of the fcfg register. 4.7.2 interrupts during flash operations before starting a ash write or erase operation, the fcfg register (see section 7.1.5) must be set up properly for the current speed. the cpu core clock is the time base for the ash write timing compensation, so it is critical that the cpu core clock speed is not changed during a ash write or erase operation. interrupts may be taken during a ash write or erase operation, if the intspd register is set up so the speed does not change when an interrupt occurs. if the ash read timing compensation is set up for a clock divisor of 1 (i.e. fastest speed), interrupts will not cause fread / iread instructions to fail, so no special precautions need to be taken to avoid violating the ash read access time. ta b le 4-9 ferase addresses (addrx=01, addrl=xx) addrh flash byte addresses 0x00 0x100 00 - 0x101fe 0x02 0x102 00 - 0x102fe ... ... 0xfe 0x1fe 00 - 0x1fffe
IP2012 / ip2022 data sheet www.ubicom.com 49 5.0 peripherals the IP2012 / ip2022 provides an array of on-chip peripherals needed to support a broad range of embedded internet applications: ?2 serializer/deserializer (serdes) units (IP2012 has one unit) ? real-time timer ? t0 timer ?2 general-purpose timers with compare and capture registers ?w atchdog timer ? 10-bit, 8-channel a/d converter ? analog comparator ?p arallel slave peripheral interface ? external memory interface (ip2022 only) all of the peripherals except the watchdog timer and the real-time timer use alternate functions of the i/o port pins to interface with external signals. 5.1 i/o ports the ip2022 contains one 4-bit i/o port (port a) and six 8- bit i/o ports (port b through port g). the IP2012 contains one 4-bit i/o port (port a), two 6-bit i/o ports (ports d and f) and four 8-bit i/o ports (ports b, c, e, and g). the four po rt a pins have 24 ma current drive capability. all the ports have symmetrical drive. inputs are 5v-tolerant. outputs can use the same 2.3?2.7v power supply used for the cpu core and peripheral logic, or they can use a higher voltage (up to 3.6v). the iovdd pins are provided for the i/o port pin output drivers. port g has a separate gvdd pin which can be used to run the port g output drivers at a voltage different from that used for the other ports, since port g must run from a 2.3?2.7v power supply. each port has separate input (rxin), output (rxout), and direction (rxdir) registers, which are memory mapped. the numbers in the pin names correspond to the bit positions in these registers. these registers allow each port bit to be individually con gured as a general-purpose input or output under software control. unused pins should be con gured as outputs, to prevent them from oating. port b has three additional registers for supporting external interrupts (see section 5.1.1). each port pin has an alternate function used to support the on-chip hardware peripherals, as listed in table 2-1. po rt a and port b support the multi-function timers timer 1 and timer 2. on the ip2022, port b, port c, and port d support the parallel slave peripheral (psp) and external memory functions. on the IP2012, port b and port c support the psp. port e and port f support the serializer/deserializer (serdes) units (only port e on the IP2012). port g supports the analog to digital converter (adc) and the analog comparator. before enabling a hardware peripheral, con gure the port pins for input or output as required by the peripheral. note: there is positive-feedback circuitry present on the i/o ports when con gured as input. this causes an input that was previously high, then subsequently tri-stated (i.e. not driven), to be actively driven by the IP2012 / ip2022 to a voltage level of approximately 1.7v, or one diode drop below (iovdd). see section 8.2 for details. figure 5-1 shows the internal hardware structure and con guration registers for each pin of a port. figure 5-1 port pin block diagram 5.1.1 port b interrupts any of the 8 port b pins can be con gured as an external interrupt input. logic on these inputs can be programmed to sense rising or falling edges. when an edge is detected, the interrupt ag for the port pin is set. the recommended initialization sequence is: 1. con gure the port pins used for interrupts as inputs by programming the rbdir register. 2. be sure all enabled interrupt pins are driven to valid logic levels, not oating. 3. select the desired edge for triggering the interrupt by programming the inted register. this may set interrupt ags. 4. nop , nop . 5. clear the interrupt ags in the intf register. 6. nop 515-030a.eps data bus port pin rxdir register 0 = output 1 = hi-z input rxout register rxin register m sync bit set u x 1 0 sync bit (fuse1) ff ff core clock sync bit clear
50 www.ubicom.com IP2012 / ip2022 data sheet 7. enable the interrupt input(s) by setting the corre- sponding bit(s) in the inte register. 8. set the gie bit. figure 5-2 shows the port b interrupt logic. port b has three registers for supporting external interrupts, the inted (section 5.1.6), intf (section 5.1.7), and inte (section 5.1.8) registers. the inted register controls the logic which selects the edge sensitivity (i.e. rising or falling edge) of the port b pins. when an edge of the selected type occurs, the corresponding ag in the intf register is set, whether or not the interrupt is enabled. the interrupt signal passed to the system interrupt logic is the or function of the and of each interrupt ag in the intf register with its corresponding enable bit in the inte register. see section 5.1.8. 5.1.2 reading and writing the ports the port registers are memory-mapped into the data memory address space between 0x020 and 0x03a. in addition, port b has three extra registers located at 0x017 through 0x019 (inted, intf, and inte), which support e xternal interrupt inputs. generally, successive read and write operations on the same i/o port is not an issue, as there are separate in an out registers for each i/o port. care must be given to ensure that enough time is allowed for data written to the out register to propagate to the in register on a given port. if this is an issue, two instructions (or four instructions if the sync bit in the fuse1 register is clear) should be inserted between any read-modify-write instruction sequences (or more nop instructions if the pin is capacitively loaded). 5.1.3 rxin registers the rxin registers are virtual registers that provide read- only access to the physical i/o pins. reading these registers returns the states on the pins, which may be driven either by the IP2012 / ip2022 or an external device. if the sync bit in the fuse1 register is clear, the states are read from a synchronization register. if an application reads data from a device running asynchronously to the IP2012 / ip2022, the sync bit should be cleared to avoid the occurrence of metastable states (i.e. corrupt data caused by an input which fails to meet the setup time before the sampling clock edge, which theoretically could interfere with the operation of the cpu). 5.1.4 rxout registers the rxout registers are data output buffer registers. the data in these registers is driven on any i/o pins that are con gured as outputs. on reads, the rxout registers return the data previously written to the data output buffer registers, which might not correspond to the states figure 5-2 port b interrupt logic

IP2012 / ip2022 data sheet www.ubicom.com 51 actually present on pins con gured as inputs or pins f orced to another state by an external device. 5.1.5 rxdir registers the rxdir registers select the direction of the port pins. f or each output port pin, clear the corresponding rxdir bit. for each input port pin, set the corresponding rxdir bit. unused pins that are left open-circuit should be con gured as outputs, to keep them from oating. f or example, to con gure port a pins ra3 and ra2 as outputs and ra1 and ra0 as inputs, the following code could be used: the second move instruction in this example writes the radir register, located at address 0x022. because port a has only four i/o pins, only the four least signi cant bits of this register are used. to drive the ra1 pin low and the ra0 pin high, the f ollowing code then could be executed: the second move instruction shown above writes the raout register, located at address 0x021. when reading the port a pins through the rain register (0x020), the upper four bits always read as zero. when a write is performed to the rxout register of a port pin that has been con gured as an input, the write is performed but it has no immediate effect on the pin. if that pin is later con gured as an output, the pin will be driven with the data that had been previously written to the rxout register. 5.1.6 inted register the inted register consists of 8 edge detection bits that correspond to the 8 pins of port b. a set bit in the inted register makes the corresponding port pin trigger on f alling edges, while a clear bit makes the pin trigger on r ising edges. 5.1.7 intf register the intf register consists of 8 interrupt ags that correspond to the 8 pins of port b. if the trigger condition f or a port b pin occurs, the corresponding bit in the intf register is set. the bit is set even if the port pin is not enabled as a source of interrupts. the interrupt service routine (isr) can check this register to determine the source of an external interrupt. if a port b pin enabled for generating interrupts has a set bit in the intf register, software must clear the bit prior to exiting to prevent repeated calls to the isr. the port b interrupt logic is asynchronous (e.g. functions without a clock in clock-stop mode). a side effect is that there is a 2-cycle delay between the instruction that clears a intf bit and the bit being cleared. this means that software must clear the bit at least 2 cycles before ex ecuting a return from interrupt ( reti ) instruction. 5.1.8 inte register the inte register consists of 8 interrupt enable bits that correspond to the 8 pins of port b. a port b pin is enabled as a source of interrupts by setting the corresponding bit in the inte register. the pin is disabled as an interrupt source by clearing the corresponding inte bit, but takes up to 1 core clock cycle for the interrupt to be disabled. 5.1.9 port con guration upon power-up on power-up, all the port control registers (rxdir) are initialized to 0xff. therefore, each port pin is con gured as a high-impedance input. this prevents any false signalling to external components which could occur if the ports were allowed to assume a random con guration at power-up. 5.2 timer 0 timer 0 is an 8-bit timer with an 8-bit prescaler intended to generate periodic interrupts for ipmodule? instances that require being called at a constant rate, such as uart and dtmf functions. when the t0tmr register counts up to ff and rolls over to 00, the t0if ag in the t0cfg register will be set, and an interrupt will occur if the t0ie and t0en bit are set (see t0cfg register description in section 7.1.20). to clear the interrupt, either the t0ie or t0en bit should be cleared, and then the t0if ag must be cleared. note: if t0if is not cleared after disabling the timer0 interrupt (t0ie = 0) or disabling timer0 (t0en = 0), it is assumed that another interrupt has occurred, and the mov w,#0x03 ;load w with the value 0x03 ;(bits 3:2 low, and bits 1:0 ;high) mov 0x022,w ;write 0x03 to radir ;register mov w,#0x01 ;load w with the value 0x01 ;(bits 3:1 low, and bit 0 ;high) mov 0x021,w ;write 0x01 to raout ;register
52 www.ubicom.com IP2012 / ip2022 data sheet interrupt will occur on the next return, or when gie is set (enabling nested interrupts - see section 3.7.2). the timer 0 interrupt is also supported in the instruction set by an option for the reti instruction which adds the w register to the t0tmr register when returning from an interrupt. figure 5-3 shows the timer 0 logic. operation of timer 0 to generate periodic interrupts: ? t0tmr = 00 when entering isr from t0 interrupt ?k eeps counting up while in isr ? add w to t0tmr with execution of reti (refer to ta- b le 3-5). interrupt frequency is adjusted by adjusting v alue loaded in w, and depending on core clock divid- er, since t0tmr runs on the system clock. if w added to t0tmr exceeds 0xff, no interrupt is taken until the t0tmr rolls over from 0xff to 0x00 again. if the t0tmr rolls over during the 3 core cycles in the re- turn from interrupt, the isr is executed again (and never again returns to mainline code as long as the isr executes the same). note: do not enable timer 0 interrupt before enabling the timer 0 itself. figure 5-3 timer 0 block diagram the control and status register for timer 0 is the t0cfg register, described in detail in section 7.1.20. note: t0if can only be asserted when t0ie = 1, t0en = 1 and t0tmr over ow occurs. 5.3 real-time timer (rttmr) the real-time timer is an 8-bit timer intended to provide a periodic system wake-up interrupt. unlike the other peripherals (except the watchdog timer and port b interrupts), the real-time timer continues to function when the system clock is disabled. for those applications which spend much of their time with the osc clock oscillator turned off to conserve power, there are 5 av ailable mechanisms to exit this mode: external reset (rst pin), reset from the watchdog timer, reset from brown-out, interrupt from a port b input, and interrupt from the real-time timer. by using an interrupt rather than reset, more of the cpu state is preserved and some reset procedures such as initializing the port direction registers can be skipped. figure 5-4 shows the real-time timer logic. (when rtclk1 is not used, it should be tied to gnd.) when the rttmr register counts up to ff and rolls over to 00, the rtif ag in the rtcfg register will be set, and an interrupt will occur if the rtie and rten bit are set (see rtcfg register description in section 7.1.9). to clear the interrupt, either the rtie or rten bit should be cleared, and then the rtif ag be cleared. note: a nop is required between a speed instruction and an instruction that enables or writes to rttmr. note: if rtif is not cleared after disabling the real-time timer interrupt (rtie = 0) or disabling the real-time timer (rten = 0), it is assumed that another interrupt has occurred, and the interrupt will occur on the next return, or when gie is set (enabling nested interrupts - see section 3.7.2). note: the system clock must be slower or equal to the r tclk clock, for a write to the rttmr to work correctly. the real-time timer is readable and writable as the r ttmr register. the control and status register for the timer is the rtcfg register, as described in section 7.1.9. the rteos bit (xcfg bit 5, see section 7.1.26) selects the sampling mode for the external input. if the rteos bit is set, the external input is over-sampled with the system clock. the cpu can always read the value in the rttmr register, if the system clock is at least twice the frequency of the external input. if the system clock source is changed to rtclk or turned off, then the rteos bit must be clear for the real-time timer to function. note: if the rteos bit is cleared, expect a 3 cycle system clock delay for the over ow interrupt, due to synchronization circuitry. if the rteos bit is clear then the external input directly clocks the real-time timer (i.e. rtclk is not ov ersampled). the real-time timer will always function whether the clock input is synchronous or asynchronous. however, the cpu cannot reliably read the value in the r ttmr register unless the rtclk clock is synchronous to the system clock (rteos=1). if the value in the rttmr register does not need to be used by the cpu (i.e. only the interrupt ag is of interest), then the rteos bit should be clear (i.e. rtclk not ov ersampled), which allows the real-time timer to function for any con guration of the system clock. 515-091c.eps 8-bit t0tmr register data bus t0ie t0if 8-bit prescaler 8 system clock t0en t0ps 3:0
IP2012 / ip2022 data sheet www.ubicom.com 53 if the value in the rttmr register needs to be used by the cpu, but the real-time timer is not required to function when the system clock is set to rtclk or turned off, then the rteos bit should be set to ensure the cpu can reliably read the rttmr register. if the value in the rttmr register needs to be used by the cpu and the real-time timer is required to function when the system clock is set to rtclk or off, then software must change the rteos bit when changing the system clock source. to read the rttmr register when the system clock is not synchronous to the rtclk, the r teos bit must be set to ensure reliable operation. before the system clock is changed to rtclk or turned off, the rteos bit must be clear (i.e. rtclk not ov ersampled) for the real-time timer to continue to function. note: when using development tools in single stepping mode, the rtss bit must be cleared and rteos must be set, otherwise the counter will behave erratically. note: care must be exercised if port b interrupts and r ttmr interrupts are enabled, because the rttmr may receive sporadic clocks during crystal startup while the system clock is waiting for wudx2:0 (see figure 3-17). figure 5-4 real-time timer block diagram 515-015b.eps osc1 rtclk1 rteos rtss 0 1 0 1 0 1 rttmr clk enable system clock "1" rteos one shot
54 www.ubicom.com IP2012 / ip2022 data sheet 5.4 multi-function timers (t1 and t2) figure 5-5 multifunction timer block diagram the IP2012 / ip2022 contains two independent 16-bit m ulti-function timers, called t1 and t2 (notated below as tx). these versatile, programmable timers reduce the software burden on the cpu in real-time control applications such as pwm generation, motor control, triac control, variable-brightness display control, sine-wave generation, and data acquisition. each timer consists of a 16-bit counter register supported by a dedicated 16-bit capture register and two 16-bit compare registers. the second compare register can also serve as capture register. each timer may use up to four e xternal pins: txcpi1 (capture input), txcpi2 (capture input), txclk (clock input), txout (output). these pins are multiplexed with general-purpose i/o port pins. the port direction register has priority over the timer con guration, so the port direction register must be programmed appropriately for each of these four signals if their associated timer functions are used. figure 5-5 is a block diagram showing the registers and i/o pins of one timer. each timer is based on a 16-bit counter/timer driven by a 15-bit prescaler. the input of the prescaler can be either the system clock or an external clock signal which is internally synchronized to the system clock. the counter cannot be directly written by software, b ut it may be cleared by writing to the txrst bit in the txctrl register. 5.4.1 timers t1, t2 operating modes each timer can be con gured to operate in one of the f ollowing modes: ? pulse-width modulation (pwm) ? timer ? capture/compare pwm mode in pwm mode, the timer can generate a pulse-width modulated signal on its output pin, txout. the period of the pwm cycle (high + low), in number of system clocks, is speci ed by the value in the txcap2h/txcap2l register. the high time of the pulse is speci ed by the v alue in the txcmp1h/txcmp1l register. pwm mode can be used to generate an external clock signal that is synchronous to the IP2012 / ip2022 system clock. for example, by loading txcmp1h/txcmp1l with 1 and txcap2h/txcap2l with 2 (the high registers must be written last for this to work), a symmetric external clock can be generated at the frequency of the system clock. in some applications, this can eliminate crystals or oscillators required to produce clock signals for other components in the system. serdes gpsi mode can also produce clock outputs. the 16-bit counter/timer counts upward, starting with the txout output driven high. after reaching the value stored in the txcmp1h/txcmp1l register minus one, at the next clock edge the txout pin is driven low. the counter/timer is unaffected by this event and continues to increment. after reaching the value stored in the txcap2h/txcap2l register minus one, at the next clock edge the timer is cleared. when the counter is cleared, the txout output is driven high, unless the txcmp1h/txcmp1l register is clear, in which case the txout pin is driven low. 515-005a.eps txcpi1 txcap1h/txcap1l register txout txcmp1h/txcmp1l register txclk d q txcpi2 txcap2h/txcap2l or txcmp2h/txcmp2l register txcnth/txcntl register 15-bit prescaler system clock system clock 0 1 txcfg1l bit 6 (oen) raout bit 3 for t1 rbout bit 3 for t2 ra2 for t1 rb2 for t2 ra0 for t1 rb0 for t2 ra1 for t1 rb1 for t2 ra3 for t1 rb3 for t2
IP2012 / ip2022 data sheet www.ubicom.com 55 there are two special cases. when the txcmp1h/txcmp1l register is clear, the txout pin is driven with a continuous low, corresponding to a duty- cycle of 0%. when the value in the txcmp1h/txcmp1l register is equal to the value in the txcap2h/txcap2l register, the txout output is driven with a continuous high, corresponding to a duty-cycle of 100%. the behavior of the timers is unde ned when the value in the txcmp1h/txcmp1l register is greater than the value in the txcap2h/txcap2l register. the timer is glitch-free no matter when the txcmp1h/txcmp1l register or the txcmp2h/txcmp2l register are changed relative to the value of the internal counter/timer. the new duty cycle or period values do not take effect until the current pwm cycle is completed (the counter/timer is reset). interrupts, if enabled through the txcfg1h register, can be generated whenever the timer output is set or cleared. if the txcmp1h/txcmp1l register is clear, or if the value in the txcmp1h/txcmp1l register is equal to the value in the txcap2h/txcap2l register, an interrupt can be generated each time the counter/timer is reset to zero. in pwm mode, the capture 1 input remains active (if enabled by the cpi1en bit in the txcfg1l register) and, when triggered, captures the current counter/timer value into the txcap1 register. the multifunction timers can be con gured to interrupt on a capture 1 event and reset the counter/timer on the ev ent. for pwm operation without capture 1, software m ust disable the capture 1 input by clearing the cpi1en bit in the txcfg1l register. timer mode this is not a separate timer mode (from the hardware point of view), but is a conceptual mode for programmers. it is the pwm mode, except that software disables the timer output by clearing the oen bit in the txcfg register. capture/compare mode in capture/compare mode, one or both of the timer capture inputs (txcpi1 and txcpi2) may be used. their pin functions must be enabled in the txcfg1 register. each capture input can be programmed in the txcfg2 register to trigger on a rising edge, falling edge, or both r ising and falling edges. when a trigger event occurs on either capture pin, the current value of the counter/timer is captured into the txcap1h/txcap1l register or the txcap2h/txcap2l register for that input pin. the counter/timers can also be con gured to reset on a txcpi1 input event, in which case the value of the counter/timer before it was reset is captured in the txcap1h/txcap1l register and the counter/timer is reset to zero. this mode is useful for measuring the frequency (or width) of external signals. by using both capture inputs and con guring them for opposite edges, the duty cycle of a signal can also be measured. to avoid w asting i/o port pins in this con guration, the cpi2en bit in the txcfg1l register is provided to internally tie the txcpi1 and txcpi2 inputs together, which frees the txcpi2 pin to be used as a general-purpose i/o port pin. an interrupt can be generated for any capture event and f or counter/timer over ows. this mode also features an output-compare function. the txcmp1h/tcmp1l register is constantly compared against the internal counter/timer. when the counter/timer reaches the value of the txcmp1h/txcmp1l register minus one, at the next counter clock the txout output is toggled. the txout output, if enabled via the oen bit, can be driven high or low by writing to the toutset and t outclr bits in the txcfg2l register. an interrupt can be enabled for this event. interrupts when a multi-function timer interrupt occurs, the corresponding interrupt ag (depending on the mode; ofif, cap2if/cmp2if, cap1if or cmp1if) in the txcfg1h register will be set, and an interrupt will occur if the tmren bit (txcfg1l register), the txie bit (tctrl register) and an interrupt source is enabled (depending on the mode; ofie, cap2ie/cmp2ie, cap1ie or cmp1ie) are set (txcfg1h register). to clear the interrupt, either the tmren bit, txie bit or the interrupt source (ofie, cap2ie/cmp2ie, cap1ie or cmp1ie) should be cleared, and then the interrupt ag (ofif, cap2if/cmp2if, cap1if or cmp1if) should be cleared. note: the interrupt ag can only be asserted when the m ulti-function timers are enabled, the timer interrupts are enabled, an interrupt source is enabled, and timer event occurs. note: if the interrupt ag is not cleared after disabling either the interrupt enable or the multi-function timer enable (tmren = 0), it is assumed that another interrupt has occurred, and the interrupt will occur on the next return, or when gie is set (enabling nested interrupts - see section 3.7.2).
56 www.ubicom.com IP2012 / ip2022 data sheet 5.4.2 t1 and t2 timer pin assignments the following table lists the i/o port pins associated with the timer t1 and timer t2 i/o functions. 5.4.3 t1 and t2 timer registers each timer has six 16-bit register pairs, which are accessed as 8-bit registers in the special-purpose register space. there is also one 8-bit register shared by both timers. txcnth/txcntl register the txcnth/txcntl register indicates the value of the counter/timer and increments synchronously with the r ising edge of the system clock. this register is read-only. the timer counter may be cleared by writing to the txrst bit in the tctrl register. reading the txcntl register returns the least-signi cant 8 bits of the internal txcnt counter and causes the most- signi cant 8 bits of the counter to be latched into the txcnth register. this allows software to read the txcnth register later and still be assured of atomicity. txcap1h/txcap1l register the txcap1h/txcap1l register captures the value of the counter/timer when the txcpi1 input is triggered. this register is read-only. reading the txcap1l register returns the least- signi cant 8 bits of an internal capture register and causes the most-signi cant 8-bits of the register to be latched into the txcap1h register. this allows software to read the txcap1h register later and still be assured of atomicity. txcmp1h/txcmp1l register in capture/compare mode, the txout output pin is toggled (if enabled by the oen bit in the txcfg1 register) when the counter/timer increments to the value in the txcmp1 register. in this mode, the value written to the txcmp1 register takes effect immediately. writing to the txcmp1l register causes the value to be stored in the txcmp1l register with no other effect. writing to the txcmp1h register causes an internal compare register to be loaded with a 16-bit value in which the low 8 bits come from the txcmp1l register and high 8 bits come from the value being written to the txcmp1h register. software should write the txcmp1l register before writing the txcmp1h register, because writing to the txcmp1h register is used as an indication that a new compare value has been written. writing to the txcmp1h register is required for the new compare value to take effect - this means that txcmp1h must be written after txcmp1l for the value to have any effect. in pwm mode, the 16-bit number latched into the internal compare register by writing to the txcmp1h register does not take effect until the end of the current pwm cycle. reading the txcmp1h or txcmp1l registers returns the previously written value whether or not the value stored in these registers has been transferred to the internal compare register by writing to the txcmp1h register. txcap2h/txcap2l or txcmp2h/txcmp2l register this register may be called the txcap2h/txcap2l register or txcmp2h/txcmp2l register. in pwm mode, this register determines the period of the pwm signal. in this mode, this register is both readable and writable. however, on writes the value is not applied until the end of the current pwm cycle. writing to the txcap2l register causes the value to be stored in the txcap2l register with no other effect. writing to the txcap2h register causes an internal compare register to be loaded with a 16-bit value in which the low 8 bits come from the txcap2l register and the high 8 bits come from the value being written to the txcap2h register. software should write the txcap2l ta b le 5-1 timer t1/t2 pin assignments i/o pin timer t1/t2 function ra0 timer t1 capture 1 input ra1 timer t1 capture 2 input ra2 timer t1 external event clock source ra3 timer t1 output rb0 timer t2 capture 1 input rb1 timer t2 capture 2 input rb2 timer t2 external event clock source rb3 timer t2 output
IP2012 / ip2022 data sheet www.ubicom.com 57 register before writing the txcap2h register, because writing to the txcap2h register is used as an indication that a new compare value has been written. writing to the txcap2h register is required for the new compare value to take effect. in pwm mode, the 16-bit number latched into the internal compare register by writing to the txcap2h register does not take effect until the end of the current pwm cycle. reading the txcap2h or txcap2l registers returns the previously written value regardless of whether the value stored in these registers has been transferred to the internal compare register by writing to the txcap2h register. in capture/compare mode, this register captures the v alue of the counter/timer when the txcpi2 input is triggered. in this mode, this register is read-only. reading the txcap2l register returns the least- signi cant 8 bits of an internal capture register and causes the most-signi cant 8-bits to be latched into the txcap2h register. this allows software to read the txcap2h register later and still be assured of atomicity. txcfg1h/txcfg1l register selects timer operation mode, pin functions, interrupts and other con guration settings. see section 7.1.21 for the description of txcfg1h and section 7.1.23 for the description of txcfg1l. txcfg2h/txcfg2l register selects capture input trigger edges, prescaler setting, and other con guration settings. see section 7.1.22 for the description of txcfg2h and section 7.1.24 for the description of txcfg2l. tctrl register unlike the other timer control registers, one tctrl register is used to synchronize both timers. setting the txrst bit clears the txcnth/txcntl register pair and the prescaler counter, which allows global synchronization of all timers on the device. there are also individual timer interrupt-enable bits. see section 7.1.25 f or description. 5.5 watchdog timer (wdt) a watchdog timer (wdt) is available for recovering from unexpected system software hang-ups. when the w atchdog timer is enabled, software must periodically clear the timer by executing a cwdt instruction. otherwise, the timer will over ow , which resets the IP2012 / ip2022 but doesn?t clear the wd bit in the pspcfg register (this bit should be set before the rst cwdt instruction is executed). any other source of reset clears the wd bit, so software can use this bit to identify a reset caused by the watchdog timer. the watchdog timer is shown in figure 5-6. figure 5-6 watchdog timer the watchdog timer is enabled by setting the wdte bit in the fuse1 register. the time period between coming out of reset or clearing the timer and timer over ow is controlled by the wdps2:0 bits in the fuse1 register, as discussed in section 3.10.2. since the watchdog timer period varies by up to 50% over temperature and voltage, the minimum timeout period selected in fuse1 that works in nominal conditions, should not be used. for instance, if the 640ms setting wo r ks in nominal conditions, the 1280ms setting should be used in production. the watchdog timer register is not visible to software. the only feature of the watchdog timer visible to software is the wd bit in the pspcfg register (see section 7.1.8). note: when using the development tools, the watchdog timer is disabled while in debug mode, except when ?run? command is issued. the break and breakx instructions suspend the watchdog timer, so that debug mode works correctly. therefore, if the watchdog feature is used, the break and breakx instructions should not be used, and the program ram should be initialized to instructions that do not include break and breakx . 515-076a.eps 8-bit timer watchdog timer reset prescaler internal rc clock (14 khz) wdte wdps 2:0 cwdt instruction
58 www.ubicom.com IP2012 / ip2022 data sheet 5.6 serializer/deserializer (serdes) there are two serdes units in the ip2022 (one unit in the IP2012), which support a variety of serial communication protocols, including gpsi, spi, uart, usb, and 10base-t ethernet. by performing data serialization/deserialization in hardware, the cpu bandwidth needed to support serial communication is g reatly reduced, especially at high baud rates. providing two units allows easy implementation of protocol conversion or bridging functions between the two high- speed serial interfaces, such as a usb to 10base-t ethernet bridge. each serdes unit uses up to 8 external digital signals: sxclk, sxrxd, sxrxm, sxrxp, sxtxm, sxtxme, sxtxp, and sxtxpe/sxoe. the signals for serdes1 are multiplexed with the port e pins, and the signals for serdes2 are multiplexed with the port f pins (ip2022 only). the port direction bits must be set appropriately for each pin that is used. not all signals are used in all protocol modes. see table 5-3 for details on signal port pin usage in various protocol modes. in addition to the digital signals, there are also two analog signals only used in 10base-t ethernet mode: sxrx+ and sxrx-. note: proper operation of the serdes requires that the core-clock be present ? don?t turn off core clock while serdes is still transmitting. serdes con guration registers the descriptions for the sxmode, sxrsync, sxsmask, sxrcfg, sxrcnt, sxtcfg, sxtmrh/sxtmrl and sxinte/sxintf registers can be found in section 7.1. note: a one cycle delay is required between consecutive read-modify-write instructions to the same serdes register (for example, clrb reg and setb reg ) 5.6.1 serdes tx/rx buffers sxrbufh/sxrbufl registers 16-bit register pair for unloading received data. the rxbf bit in the sxintf register indicates when new data has been loaded into this register. if the corresponding bit in the sxinte register is set, an interrupt is generated. sxtbufh/sxtbufl registers 16-bit register pair for loading data to be transmitted. the txbe bit in the sxintf register indicates when the data has been transmitted and the register is ready to be loaded with new data. if the corresponding bit in the sxinte register is set, an interrupt is generated. regardless of the number of bits to be transmitted, both the high and low registers need to be written to initiate transmission. 5.6.2 serdes con guration software prepares a serdes unit to receive data by programming the receive shift count register (sxrcfg) and the clock select bits in the sxmode register appropriately for the selected protocol. the sxrcfg register is copied to an internal counter, and when that n umber of bits of data has been received, the received data is loaded into the sxrbuf register. in 10base-t, gpsi, or usb mode, when an eop is detected, the sxrcnt register is loaded with the number of bits actually received, the eop bit of the sxintf register is set, and the data bits are loaded into the sxrbuf register. the rxbf bit in the sxinte register can be set to enable an interrupt on this event. the sxtxp and sxtxm pins correspond to the differential outputs of the usb or ethernet bus. other serial protocols require only one output pin, which is sxtxp by default. the sxtxp and sxtxm pins have high current outputs for driving ethernet magnetics directly without the use of transceivers. when the clock select register is programmed with the v alue for 10base-t, the transmit pre-emphasis requirement enables the sxtxpe and sxtxme outputs, which have a 50ns-delayed version of the transmit output that is resistively combined outside the chip before driving the magnetics. f or transmitting, software must specify the number of bits to transmit (speci ed in the sxtcfg register) and load the data in the sxtbuf register. this data is then transferred to an internal register, from which it is serially shifted out to the transmit logic. the txbe bit in the sxinte register can be set to enable an interrupt when the data has been transferred from the sxtbuf register. when there is a transmit buffer underrun event (i.e. all of the data has been shifted out from the internal register, b ut the sxtbuf register has not been reloaded), an eop condition is generated on the sxtxp and sxtxm outputs after an internal counter decrements to zero. the txeop bit in the sxinte register can be set to enable an interrupt when an underrun event occurs. f or protocols other than usb and ethernet, the eop generator is bypassed.
IP2012 / ip2022 data sheet www.ubicom.com 59 5.6.3 serdes interrupts figure 5-7 shows the interrupt logic for the two serdes units. for a detailed description of the sxinte/sxintf register bits, refer to section 7.1.10. figure 5-7 serdes interrupt logic

60 www.ubicom.com IP2012 / ip2022 data sheet 5.6.4 protocol modes ta b le 5-2 shows the features which are enabled for each protocol, as controlled by the prs3:0 bits in the sxmode register. these features affect which registers and register elds are used, for example the sxrsync register is only used in the usb and 10base-t modes. the protocol mode also affects the signal usage, as shown in table 5-3. pins not used for protocols can be used for general i/o. ? sxclk - serial clock in spi or gpsi slave modes, optional external serdes clock input for usb or ua rt modes. ? sxrxp - positive-side differential input (usb only), slave select (for spi slave), or data valid (gpsi). ? sxrxm - negative-side differential input (usb only). ? sxrxd - serial data for usb, uart, spi and gpsi modes (10base-t ethernet only when comparator is used). ? sxtxpe - positive-side delayed differential output for pre-emphasis (10base-t ethernet), output enable for e xternal transceiver (usb), or data valid for gpsi mode. ? sxtxp - positive-side differential output (10base-t ethernet and usb modes), or serial data (uart, spi and gpsi modes). ? sxtxm - negative-side differential output (10base-t ethernet and usb modes), transmit clock (gpsi slave), or transmit and receive clock (gpsi master). ? sxtxme - negative-side delayed differential output f or pre-emphasis (10base-t ethernet), or txbusy in gpsi mode. ? sxrx+ - positive-side analog differential input, used f or 10base-t ethernet squelch function. ? sxrx- - negative-side analog differential input, used f or 10base-t ethernet squelch function. ta b le 5-2 protocol features prs3:0 mode encoding method differential or single-ended? synchronization register enabled? eop generation/ detection? bit stuffing/ unstuffing? pre-emphasis outputs enabled? 0001 10base-t manchester differential yes yes n/a yes 0010 usb bus nrzi differential yes yes yes n/a 0011 uart none single-ended no n/a n/a n/a 0101 spi none single-ended no yes n/a n/a 0110 gpsi none single-ended no yes n/a n/a ta b le 5-3 serdes protocol modes and pin usage signal names sxclk sxrxp sxrxm sxrxd sxtxpe sxtxp sxtxm sxtxme sxrx+ sxrx- serdes1 pins re0 re1 re2 re3 re4 re5 re6 re7 rg5 rg4 serdes2 pins (ip2022 only) rf4 rf5 rf6 rf7 rf0 rf1 rf2 rf3 rg7 rg6 mode 10base-t ethernet --- rxd note 1 txd+ (o) tx+ (o) tx- (o) txd- (o) rx+ (i) rx- (i) usb bus optional vp (i) vm (i) rcv (i) oe (o) vpo (o) vmo (o) - - - ua rt optional - - rxd - txd - - - - spi master sclk - - di (i) - do (o) - - - - slave sclk ss (i) - di (i) - do (o) - - - - gpsi master - txen (o) - txd (o) rxen (i) rxd (i) txclk/ rxclk (o) txbusy (i) -- slave rxclk (i) txen (o) - txd (o) rxen (i) rxd (i) txclk (i) txbusy (i) -- 1. i. o. used in comparator mode only. input output
IP2012 / ip2022 data sheet www.ubicom.com 61 5.6.5 10base-t ethernet hardware each serdes unit provides 4 transmission digital signals: sxtxm, sxtxme, sxtxp, and sxtxpe. these signals for serdes1 are multiplexed with the port e pins, and the signals for serdes2 (ip2022 only) are m ultiplexed with the port f pins. the differential receive signals are multiplexed on port g pins for 10base-t ethernet mode: sxrx+ and sxrx-. the port direction bits m ust be set appropriately for each pin that is used. other unused pins from serdes and port g remain available f or other functions usage. see table 5-4 for details on signal port pin usage in various protocol modes. note: proper operation of the 10base-t requires that the core-clock be present as serdes master clock is derived from it - don't turn off core clock while serdes is still transmitting. figure 5-8 shows the clock/data separation and end-of- pa ck et (eop) detection logic of a 10base-t receiver unit. the sxrxp and sxrxm pins correspond to the differential inputs. providing both inputs allows sensing of an eop condition. to set up a serdes unit for 10base-t ethernet, the input data from a differential line receiver is connected to the sxrx+ and sxrx- input. the signals designated tx+, tx-, txd+, and txd- correspond to the sxtxp, sxtxm, sxtxpe, and sxtxme pins of the corresponding serdes. these pins are connected to an rj45 jack through a transformer with terminations. figure 5-8 clock/data separation and eop detection figure 5-9 shows an example circuit. rtxpe, rtxme, r txp, rtxm and rl values vary depending on the ethernet magnetics used. please refer to ip2022 native ethernet application notes for more details. f or 10base-t ethernet operation, each serdes is equipped with a squelch circuit for discriminating between noise, link pulses, and data. link pulses are sent periodically to keep the channel open when no data is being transmitted. the squelch circuit handles link pulse detection, link pulse polarity detection, carrier sense, and eop detection. the 10base-t mode requires only a x ed sfd (start of frame) pattern, so the sfd pattern for 10base-t is hardwired to be 11010101 and the synchronization pattern register (sxrsync) is used to con gure features of 10base-t other than sfd pattern. refer to section 7.1.14 for detailed information. the incoming data stream, after passing through the polarity inversion logic (which can be turned on or off under software control) is compared to the synchronization pattern. once a match is f ound, an internal counter is set to zero and data is shifted into a shift register. the synchronization matching operation is then disabled until an eop condition is detected, because the synchronization pattern potentially could be embedded in the data stream as valid data. 515-003e.eps clock/data separation and start condition detection receive polarity reversal bit receive data data eop eop detection synchronization pattern register (sxrsync) sxrxd input post-pll clock osc clock ethernet squelch circuit sxrx+ sxrx- sxclk sxmode
62 www.ubicom.com IP2012 / ip2022 data sheet figure 5-9 ethernet interface example figure 5-10 shows the receive data paths. when an eop is detected the sxrcnt register is loaded with the n umber of bits actually received, the eop bit of the sxintf register is set, and the data bits are loaded into the sxrbuf register. the rxbf bit in the sxinte register can be set to enable an interrupt on this event. the data encode block performs 10base-t manchester encoding. the encoded tx signal are sent to tx pins in a differential mode. the encode block is bypassed for all other protocols. the sxtxp and sxtxm pins have high current outputs for driving ethernet magnetics directly without the use of transceivers. the pre-emphasis tx outputs are enabled on sxtxpe and sxtxme outputs, which have a 50ns-delayed and inverted version of the transmit outputs. the resistively combined tx outputs outside the chip are used to drive the magnetics. the output pins of the serializer are driven low when not transmitting. figure 5-11 shows the transmit data paths. for transmitting, software must specify the number of bits to transmit (speci ed in the sxtcfg register) and load the data in the sxtbuf register. this data is then transferred to an internal register, from which it is serially shifted out to the transmit logic. the txbe bit in the sxinte register can be set to enable an interrupt when the data has been transferred from the sxtbuf register. when there is a transmit buffer underrun event (i.e. all of the data has been shifted out from the internal register, but the sxtbuf register has not been reloaded), an eop condition is automatically generated on the tx output pins after an internal counter decrements to zero. the txeop bit in the sxinte register can be set to enable an interrupt when an underrun event occurs. ta b le 5-4 10base-t ethernet interface signal and port pin usage 10base-t signal name serdes signal name serdes1p in name serdes2 pin name (ip2022 only) direction description tx+ sxtxp re5 rf1 output plus-side differential output tx- sxtxm re6 rf2 output minus-side differential output txd+ sxtxpe re4 rf0 output plus-side differential output with pre- emphasis txd- sxtxme re7 rf3 output minus-side differential output with pre- emphasis rx+ sxrx+ rg5 rg7 input plus-side analog differential input, used f or 10base-t ethernet squelch function rx- sxrx- rg4 rg6 input minus-side analog differential input, used f or 10base-t ethernet squelch function clock recovery rx+ rx- manchester decoding coding serializer/deserializer rj45 data encoder data decoder manchester ip2022 or IP2012 rtxpe squelch sxrx- sxrx+ sxtxpe ethernet magnetics (lpf required) rl sxtxm sxtxme sxtxp txd+ txd- tx- tx+ rtxme rtxm rtxp 515-064d.eps
IP2012 / ip2022 data sheet www.ubicom.com 63 figure 5-10 receive data paths figure 5-11 transmit data paths software the serdes 10base-t mode is designed to run at a x ed 8x oversampling for line receiver. so a x ed 80mhz master must be con gured through sxmode. the core pll clock multiplier must be programmed to be an integer m ultiple of 80mhz for 10base-t operation. the received data stream is used, together with the clock recovery circuit, to recover the original transmit clock and data. t ypical operation with ubicom's sdk uses a 4.8 mhz crystal with a pll post-divide by 2 to yield 120 mhz core operation, or a 3.2 mhz crystal with no pll post-divide to yield 160 mhz operation. software must perform the following functions: ?p olarity detection and reversal. ? carrier sense. ?j abber detection. ? link integrity test and link pulse generation. ? random back off in case of collision. ? when a collision is detected, sending a 32-bit jam se- quence. collisions can be detected by positive detec- tion of carrier sense during active transmission. ?f ormation of ethernet packet by putting the preamble, sfd, destination address, source address, length/type, mac client data into the transmit buffer. fr ame check computation can be done in software or through the lfsr units (see section 5.9). ?m ac layer functions.
!"" !#$ ! &!$ ' 515-018a.eps transmit configuration register (sxtcfg) t ransmit clock data encoder transmit buffer register (sxtbuf) data bus sxtxpe pre-emphasis eop generator sxtxme sxtxp sxtxm txbe, txeop transmit interrupt
64 www.ubicom.com IP2012 / ip2022 data sheet 5.6.6 usb each serdes provides support for usb revision 1.1 host and device modes of operation. hardware to set up a serdes unit for usb mode, the received data output of the usb transceiver should be connected to sxrxd. the vp and vm pins of the transceiver are connected to the sxrxp and sxrxm pins to allow detection of the eop condition. figure 5-12 shows the connections required between an external usb transceiver and the IP2012 / ip2022. table 5-6 shows the mapping of usb signals to the serdes pins. if desired, an external clock source can be connected to the sxclk pin. for additional hardware con guration information, please refer to usb reference design available. software the sxmode register must be programmed with values f or the desired usb mode, full speed or low speed. serdes clock dividers, sxtmrh and sxtmrl, also need to be programmed to generate the appropriate frequency according to the usb submode selection. table 5-7 shows the pll clock frequencies required for the low and full speed modes of the usb mode. for example, if the pll clock is 240 mhz, it can be programmed at 48 mhz f or full speed with a divisor of 4 (=5). a divisor of 39 will make it suitable for low-speed operation. if external clock mode is selected, the clock divisor value is ignored and the clock is used directly for usb operation. in usb mode, the serdes uses two registers, sxrsync and sxsmask, to detect the sync pattern marking the beginning of a usb data stream. this sequence is de ned to be ?7 zeros and a single 1? by the usb speci cation, and only the last 3 bits need to be matched to start receiving data, also de ned in the speci cation. in order to achieve this, sxrsync needs to be programmed with 0x80 and sxsmask needs to be programmed with 0xe0. receive behavior is controlled by the sxrcfg and sxrcnt registers. for usb operation, the higher 3 bits of sxrcfg should be set to zero, and the lower 5 bits should be set to the desired number of bits received, usually 8 or 16. sxrcnt should be cleared to make sure receive is performed lsb rst. once the serdes matches the usb sync pattern, the internal receive count is reset to zero and the serdes receives bits from the line until either the desired count is received or an eop is encountered, at which point the received data is transferred to the serdes rx data registers. if more data is coming in, the procedure will be repeated. software is responsible for reading the data from the data registers before the next write by the hardware. notice that this will be a short time, if rxcfg is con gured with a small receive count, or an eop is received before the desired count is reached. when the eop is received, the serdes remains idle until the next match of the sync pattern. tr ansmit behavior is controlled by the sxtcfg register. f or proper usb operation, the higher 3 bits should be set to 100, and the lower 5 bits should be set to the desired n umber of bits transmitted. transmit can be initiated by writing to the serdes tx data registers. notice that both registers must be written even if the number of bits to transmit is less than 8. if the transmit count needs to be changed, it must be changed before the tx data registers are written. for continued transmission, tx data registers have to be written before the tx bit count is reached. otherwise, the serdes automatically inserts the eop signaling. while receiving data, the clock/data separation circuit performs nrzi decoding, after which bit unstuf ng is performed. this means every bit after a series of six consecutive ones is dropped. on transmit, the serdes performs bit stuf ng, and the clock/data separation circuit nrzi encodes the data. note: while con gured for usb mode, the serdes cannot be con gured to interrupt on carrier status (rxcrs, sxrcnt bit 5; see section 7.1.13). ta b le 5-5 shows the function of serdes status ags in usb mode. see also section 7.1.10. ta b le 5-5 summary of status flags in usb mode flag usb mode function rxerror this bit indicates the presence of 7 ones in the usb bit stream. rxeop this bit indicates the presence of eop signaling, which is 2 bit times of se0 and 1 bit time of j condition on the bus. synd this bit indicates that serdes successfully matched a usb sync pattern as con gured in the sxsync register. txbe this bit indicates that new data can be written to the tx data registers to continue uninterrupted data stream. txeop this bit indicates that an eop condition w as generated to signal the end of the usb data stream. tx data registers should be written with the sync pattern to start a new stream once this condition occurs.
IP2012 / ip2022 data sheet www.ubicom.com 65 software must perform the following functions to implement the usb protocol for a device: ? crc generation and checking (can be done using the lfsr, section 5.9). ? detecting reset of the device function, which is indi- cated by 10 milliseconds of a single-ended zero (se0) condition on the bus. ? detecting the suspend state, which is indicated by more than 3 milliseconds of idle. software muse make sure that the suspend current of 500 ua will be drawn after 10 milliseconds of bus inactivity. ?f ormation of the usb packet by putting the sync, pid, and data into the transmit data registers and setting the proper count. ? endpoint and device management and other higher level protocol tasks. timing considerations usb relies on certain timing limitations for error detection and recovery. response time requirements are speci cally harder to meet. isr for usb needs to be carefully structured to satisfy these requirements, and this is possible because of IP2012 / ip2022's deterministic isr execution times. the time from the se0 on bus to the rxeop indication is about 208 ns. the time from writing to tx data registers and the data put on the bus is about 125 ns. software tasks like address, error, crc checking, and determining the endpoint response have to be carefully timed and cycle counted to assure the required timing limitations are satis ed. figure 5-12 usb interface example sxlink- pulse txidle in usb mode. this bit indicates whether the serdes is actively transmitting data. rxbf this bit indicates that rx data registers are written with new data and should be read before the next desired amount of bits are received. rxxcrs this bit is a live status indicator in usb mode. if set, the serdes is receiving data into the shift register, but there might not be any data in the data registers yet. ta b le 5-5 summary of status flags in usb mode flag usb mode function pdiusbp11a sxrxd ip2022 or IP2012 515-034c.eps sxrxm sxtxp sxtxm d+ d- usb bus sxrxp + - rcv vm vpo vmo vp sxtxpe oe ta b le 5-6 usb interface signal usage usb signal name serdes signal name serdes1 pin name serdes2 pin name (ip2022 only) direction description vp sxrxp re1 rf5 input plus-side differential input vm sxrxm re2 rf6 input minus-side differential input vpo sxtxp re5 rf1 output plus-side differential output vmo sxtxm re6 rf2 output minus-side differential output
66 www.ubicom.com IP2012 / ip2022 data sheet oe sxtxpe re4 rf0 output output enable rcv sxrxd re3 rf7 input receive data clock sxclk re0 rf4 input external clock input (optional) ta b le 5-6 usb interface signal usage (continued) usb signal name serdes signal name serdes1 pin name serdes2 pin name (ip2022 only) direction description ta b le 5-7 required clock frequencies from serdes clock in usb mode protocol receive usb 1.1 full speed 48 mhz usb 1.1 low speed 6 mhz
IP2012 / ip2022 data sheet www.ubicom.com 67 5.6.7 uart f or uart operation, two internal divide-by-16 circuits are used. based on the clock source (either internal or e xternal), the receive section and the transmit section use two divided-by-16 clocks that potentially can be out of phase. this is due to the nature of the uart bus transfers. the receive logic, based on the 16x bit clock (the clock source chosen by user), will sample the incoming data for an falling edge. once the edge is detected, the receive logic counts 8 clock cycles and samples the number of bits speci ed in the sxrcnt register using the bit clock (which is obtained by dividing the clock source by 16). hardware figure 5-13 shows an example circuit to connect the serdes in uart mode. table 5-8 shows the uart signal to port pin usage. software to set up a serdes unit for uart mode, select uart mode in the prs3:0 bits of the sxmode register. this causes the data to be clocked in after a valid start bit is detected. make sure that the polarity selected by the rporev bit in the sxrcfg register and the tporev bit in the sxtcfg register match the polarity provided by the rs-232 transceiver. (most of them are inverted.) make sure the bit order is compatible with the data format (rs- 232 uses lsb- rst bit order). the receiver uses 16x ov ersampling, so select a serdes clock divisor (see section 7.1.17 for information on the sxtmrh/l registers) that is 16 times the desired baud rate. to operate in uart mode, depending on the application, either transmit or receive can be performed rst. in both cases, the con guration register needs to be programmed with a bit count that is appropriate for the format. the bit count depends on the number of data bits, stop bits, and parity bits. the start bit is included in the bit count. the receiver does not check for the presence of stop bits. to detect framing errors caused by missing stop bits, increase the receiver?s bit count (i.e. the rxscnt eld in the sxrcfg register) and test the trailing bit(s) in software. figure 5-13 uart interface example rs-232 transceiver sxrxd ip2022 or IP2012 515-094a.eps sxtxp rxin txout rs-232 rxout txin ta b le 5-8 uart interface signal usage uart signal name serdes signal name serdes1 pin name serdes2 pin name (ip2022 only) direction description rxd sxrxd re3 rf7 input receive data txd sxtxp re5 rf1 output transmit data
68 www.ubicom.com IP2012 / ip2022 data sheet 5.6.8 spi hardware figure 5-14 shows example circuits to connect the serdes in spi mode. table 5-10 and table 5-11 show the spi signal to port pin usage. con guration the serdes can be con gured for either master or slave mode: sxrcfg[7] = 0: slave sxrcfg[7] = 1: master the serdes sck idle-level (i.e. when ss is de-asserted) can be con gured: sxmode[4] (cpol) = 0: idle is low sxmode[4] (cpol) = 1: idle is high finally, the serdes can be con gured for the phase relationship of the sdo/sdi pins with respect to the sck edge: sxmode[3] (cpha) = 0: sdo is set up by the other device a half clock period before the rst edge following the assertion of ss*. therefore sdi will be sampled by this device (the slave) on the rst edge (transition). sxmode[3] (cpha) = 1: sdo is set up by the other device on the rst edge f ollowing the assertion of ss*. therefore sdi will be sampled by this device (the slave) on the second edge (transition). note: the use of the term "edge" in the above paragraphs implies any transition, not a speci c type (i.e. rising or f alling) of transition. therefore, " rst edge" implies a rising edge when cpol=0, and implies a falling edge when cpol=1. in the spi scheme implemented by motorola, which the IP2012 / ip2022 follows, data being output on sdo and data being sampled on sdi always occur on opposing edges of the clock, on either master or slave. transmitting and sampling on the same-edge of the clock is not supported by the serdes. cpol, in conjunction with cpha, determines which clock edges the serdes will be using to output and sample data on, as given by table 5-9. when the serdes is con gured as a slave, the state of the sdo line when ss* is de-asserted will be determined by the value in the rxout gpio register for that pin, which the user can con gure. figure 5-14 spi interface examples ta b le 5-9 serdes output and sample con guration cpol cpha 00 output on falling, sample on rising 01 output on rising, sample on falling 10 output on rising, sample on falling 11 output on falling, sample on rising spi master sxclk ip2022 or IP2012 (spi slave) 515-095b.eps sxtxp(do) sclk di sxrxd(di) do sxrxp ss or spi slave sxclk ip2022 or IP2012 (spi master) sxtxp(do) sclk di sxrxd(di) do gpio ss sclk do di ss sclk do di ss
IP2012 / ip2022 data sheet www.ubicom.com 69 figure 5-15 spi signal timing ta b le 5-10 spi master interface signal usage spi device signal name IP2012 / ip2022 spi signal name serdes signal name serdes1 pin name serdes2 pin name (ip2022 only) direction description sclk sclk sxclk re0 rf4 output serial clock output in mas- ter mode, input in slave mode do di sxrxd re3 rf7 input receive data di do sxtxp re5 rf1 output transmit data ss ss gpio re1 rf5 output slave select pin used in slave mode only (master select handled by software) ta b le 5-11 spi slave signal usage spi device signal name IP2012 / ip2022 spi signal name serdes signal name serdes1 pin name serdes2 pin name (ip2022 only) direction description sclk sclk sxclk re0 rf4 input serial clock output in mas- ter mode, input in slave mode do di sxrxd re3 rf7 input receive data di do sxtxp re5 rf1 output transmit data ss ss sxrxp re1 rf5 input slave select pin used in slave mode only (master select handled by software) 12 3 4 56 7 8 sck cycle # sck (cpol = 0) sck (cpol = 1) sample input (cpha = 0) data out sample input (cpha = 1) data out ss (to slave) msb 6 5 4321lsb msb 654321 lsb 515-098.eps
70 www.ubicom.com IP2012 / ip2022 data sheet 5.6.9 gpsi hardware figure 5-16 shows example circuits to connect the serdes in gpsi (general purpose serial interface) mode. table 5-12 shows the gpsi signal to port pin mapping in master mode, and table 5-13 shows the gpsi signal to port pin mapping in slave mode. software gpsi is a general-purpose, point-to-point, full-duplex serial bus protocol. only two devices are allowed to exist on a bus. the gpsi phy device is responsible for maintaining bus timing by driving two continuously r unning clocks, txclk and rxclk. the device that does not drive the clocks is the mac device. the txen and txd signals are synchronized to the txclk clock. the rxd and rxen signals are synchronized to the rxclk clock. the collision and txbusy signals do not participate in actual data transfer on the gpsi bus. collision and txbusy provide additional ow control capabilities for the software device driver. the collision signal is used to indicate that a phy device has detected a collision condition. this signal is only useful when the serdes is connected to a phy device or acting as a phy device. the txbusy signal is used by a gpsi device to indicate that the device is currently busy, and that another device should not attempt to start a data transfer. refer to sxrcnt register bit 5. refer to section 7.1.10 through section 7.1.17 for detailed con gurations. example: to get the pll clock divided by 2 out on re6: s1mode=63 s1rcfg=80 s1tcfg=80 figure 5-16 gpsi interface examples 515-096c.eps or gpsi master sxclk ip2022 or IP2012 (gpsi slave) sxtxp txclk rxd sxrxd txd sxrxp txen sxtxpe rxen sxtxm rxclk gpio col sxtxme txbusy gpsi slave ip2022 or IP2012 (gpsi master) sxtxp rxclk txd sxrxd rxd sxrxp rxen sxtxpe txen sxtxm txclk gpio col gpio txbusy rxclk txd rxd rxen txen txclk col txbusy rxclk rxd txd txen rxen txclk/rxclk col txbusy
IP2012 / ip2022 data sheet www.ubicom.com 71 note: in gpsi master mode, the sxtxm serdes pin should be used by the gpsi slave for both txclk and rxclk inputs ta b le 5-12 IP2012 / ip2022 gpsi master interface signal usage gpsi slave signal name IP2012 / ip2022 gpsi signal name serdes signal name serdes1 pin name serdes2 pin name (ip2022 only) IP2012 / ip2022?s direction description txclk and rxclk txclk and rxclk sxtxm re6 rf2 output transmit and receive clock txd rxd sxrxd re3 rf7 input transmit data txen rxen sxrxp re1 rf5 input transmit data valid rxd txd sxtxp re5 rf1 output receive data rxen txen sxtxpe re4 rf0 output receive data valid txbusy txbusy gpio - - output indicates a data transfer in progress (handled by soft- w are) collision collision gpio - - output indicates a collision at phy layer (han- dled by software) ta b le 5-13 IP2012 / ip2022 gpsi slave interface signal usage gpsi master signal name IP2012 / ip2022 gpsi signal name serdes signal name serdes1 pin name serdes2 pin name (ip2022 only) IP2012 / ip2022?s direction description txclk rxclk sxtxm re6 rf2 input transmit clock rxd txd sxtxp re5 rf1 output transmit data rxen txen sxtxpe re4 rf0 output transmit data valid txclk rxclk sxclk re0 rf4 input receive clock txd rxd sxrxd re3 rf7 input receive data txen rxen sxrxp re1 rf5 input receive data valid txbusy txbusy sxtxme re7 rf3 input indicates a data transfer in progress (handled by soft- w are) collision collision gpio - - input indicates a collision at phy layer (han- dled by software)
72 www.ubicom.com IP2012 / ip2022 data sheet 5.7 analog to digital converter (adc) the on-chip a/d converter has the following features: ? 10-bit adc (when vref > 2.3v) ?8 input channels ? 48 khz maximum sampling rate ? one-shot conversion. ? optional external reference voltage ? vmax = avdd (max 2.7v) ? result returned in the adch and adcl registers figure 5-17 shows the a/d converter circuitry. the adc input pins use alternate functions of the port g pins. the result of an adc sample is the analog value measured on the selected pin. to correctly read an external voltage, the pin being sampled must be con gured as an input in the port direction register (i.e. the rgdir register). if the pin is con gured as an output, then the result will indicate the v oltage level being driven by the output buffer. the rg1 and rg2 port pins are also used as the analog comparator input pins. the result of sampling the rg1 or rg2 pins will be correct whether or not the comparator is operating. the rg0 pin is also used as the comparator output pin. if the comparator is enabled, then sampling the rg0 pin will indicate the voltage level being driven by the comparator. the rg3 pin is multiplexed with the external reference voltage. figure 5-17 a/d converter block diagram 5.7.1 adc reference voltage the reference voltage (vref) can come from either the rg3 port pin or from the avdd supply voltage. if avdd is used, the rg3 port pin may be used as a channel of analog input or as a general-purpose port pin. vref de nes a voltage level which reads as one increment of resolution below the full-scale voltage. the full-scale v oltage reads as 0x3ff, so the vref voltage reads as 0x3fe and the a/d converter resolution is 10 bits. table 5-14 shows the values reported at the upper and lower limits of the adc input voltage range. 5.7.2 a/d converter registers adctmr register the adctmr register (see section 7.1.2) is used to specify the number of system clock cycles required for a delay of 1736 ns, which is used to provide the 1.152mhz (48 khz 24) clock period reference clock for the a/d converter. f or example, at a system clock frequency of 120 mhz, the timer register should be set to 53 ((120 mhz/1.152 mhz)/2). the minimum value that may be loaded into the adctmr register is 2, so the system clock must be at least 24 times the adc sampling frequency for the adc to function. adccfg register the a/d converter con guration register (adccfg) provides the control and status bits for the a/d converter, as shown in section 7.1.1.

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IP2012 / ip2022 data sheet www.ubicom.com 73 5.7.3 using the a/d converter the following sequence is recommended: 1. set the adctmr register to the correct value for the system clock speed. 2. load the adccfg register to specify the channel and set the adcgo bit. setting the adcgo bit en- ables and resets the adc timer. 3. after a period of time (24 timer over o ws = 20.8 s) the conversion will complete, the adcgo bit will be cleared, and the adc timer will be disabled. 4. a timer-based interrupt service routine can detect or assume the adcgo bit has been cleared and read the adc value. 5. another load to the adccfg register can then be used to start another conversion. 5.7.4 adc result justi cation the 10 bits of the adc value can be mapped to the 16 bits of the adch/adcl register pair in three different ways, as shown in table 5-15. in this table, the numbers in the cells represent bit positions in the 10-bit adc value, z represents zero (as opposed to bit position 0), and -9 represents the inversion of bit position 9. 5.8 comparator the IP2012 / ip2022 has an on-chip analog comparator which uses alternate functions of the rg0, rg1, and rg2 port pins. the rg1 and rg2 pins are the comparator negative and positive inputs, respectively, while the rg0 pin is the comparator output pin. to use the comparator, software must program the port direction register (rgdir) so that rg1 and rg2 are inputs. rg0 may be set up as a comparator output pin. figure 5-18 analog comparator the comparator enable bits are cleared on reset, which disables the comparator. to avoid drawing additional current during power-down mode, the comparator should be disabled before entering power-down mode. a 50 mv h ysteresis is applied between the inputs, when the cmphys bit is set in the cmpcfg register. 5.8.1 cmpcfg register the cmpcfg register is used to enable the comparator, to read the output of the comparator internally, to enable the output of the comparator to the comparator output pin, and to enable the hysteresis. section 7.1.3 shows the bits in this register. ta b le 5-15 justi cation of the adc value mode adch register bits adcl register bits 7654321076543210 left justi ed 9876543210zz zzzz right justi ed zzzzzz 9876543210 signed -9 -9 -9 -9 -9 -9 -9 8 7 6 5 4 3210

74 www.ubicom.com IP2012 / ip2022 data sheet 5.9 linear feedback shift register (lfsr) figure 5-19 lfsr block diagram f our linear feedback shift register (lfsr) units provide hardware support for the computation-intensive inner loops of algorithms commonly used in data communications, such as: ? cyclic redundancy check (crc) ? data scrambling ? data whitening ? encryption/decryption ? hashing the lfsr units implement a programmable architecture, which can be adapted for algorithms used by the bluetooth, ethernet, homeplug, homepna, homerf, ieee 802.11, and usb communication protocols. figure 5-19 is a block diagram of the lfsr architecture. the 40-bit residue register and its surrounding circuits are the computational core of an lfsr unit. on every clock cycle, 39 output bits from the register are available at the input for performing a shift operation or a polynomial add/subtract-and-shift operation. four 40-bit multiplexers at the output of the residue register allow selecting up to f our terms of the register for feedback into the input (d0), polynomial operation control (poly_xor_en), and output (dout) bit streams. a fth multiplexer is only used f or generating the output bit stream. the polynomial and residue registers are mapped as ve 8-bit registers. the mapping of the residue register is controlled by the ml_out bit of the lfsrcfg3 register, as shown in figure 5-20. figure 5-20 mapping of the residue register input data is shifted serially out of the 16-bit datain register, which can be programmed to provide the data lsb- rst or msb- rst. output data is shifted serially lsb- rst into the 16-bit dataout register. polynomial register (polyx) residue register (resx) 1..39 1..39 0..39 0 0 0 1 0..38 0..39 fb1 40:1 0..39 fb2 40:1 0..39 fb3 40:1 0..39 dout 40:1 d0 source gating poly source gating dout source gating 16-bit dataout register datain register 515-082b.eps d0 poly_xor_en dout din 0..39 fb4 40:1 40 39 39 1 1 1 1 1 1 1 39

IP2012 / ip2022 data sheet www.ubicom.com 75 a 32-bit rescmp register (not shown) can be used to compare the result in the residue register against an e xpected value. when ml_out is set, residue register bits 0:31 are compared against rescmp bits 0:31. when ml_out is clear, residue register bits 39:8 are compared to rescmp bits 0:31, respectively. if there are bits in the residue register which do not participate in the programmed lfsr operation, be sure that the corresponding bits in the rescmp register are initialized to the same values as these non-participating bits. each lfsr unit has three con guration registers (lfsrcfg1, lfsrcfg2, and lfsrcfg3) for various control and status bits. the hl_trigger bit in the lfsrcfg3 register controls whether operation of the lfsr unit is triggered by a write to the high byte or the low b yte of the datain register (i.e. datainh or datainl). the operation then proceeds for some number of cycles programmed in the shift_count3:0 eld of the lfsrcfg1 register. completion of the operation is indicated when the done bit in the lfsrcfg1 register is set. (alternatively, software can wait 1 cycle/bit of datain before reading the result.) an autoloading option is available for each lfsr unit to load the datain register automatically from the serdes rx buffers (sxrbuf register of the corresponding serdes unit). lfsr0 and lfsr2 are paired with serdes1, and lfsr1 and lfsr3 are paired with serdes2. three registers in data memory are used to access the lfsr register banks, as shown in table 5-16. the lfsra register is loaded to point to a speci c lfsr unit and a register pair within the unit. the lfsra register has the format shown in figure 5-21 figure 5-21 lfsra register only 0, 1, 2, and 3 are valid as the unit, lfsra bits 7 and 6 = don?t care. the valid encodings for the index are shown in table 5-17. the lfsr registers do not support consecutive read- modify-write operations. for example, the following instruction sequence loads unpredictable values: clrb lfsrh,7 clrb lfsrh,4 5.9.1 lfsrcfg1 register figure 5-22 lfsrcfg1 register ? set_res ?set to initialize the residue register to all ones (write-only, reads as zero). ? done ?clear while the lfsr is busy, set when the operation is completed (read only). ? cmp_res ?set if last lfsr operation result matched contents of rescmp register (read only). ? shift_count3:0 ?speci es number of bits to shift, load with n for an operation of n+1 shifts. ta b le 5-16 lfsr registers in data memory address name description 0x23 lfsrh high data byte 0x27 lfsrl low data byte 0x2b lfsra address register 7430 unit3:0 index3:0 ta b le 5-17 lfsra register index encoding index3:0 high byte (lfsrh) low byte (lfsrl) 0x0 datainh datainl 0x1 dataouth dataoutl 0x2 fb2 fb1 0x3 lfsrcfg2 res4 0x4 res3 res2 0x5 res1 res0 0x6 fb4 fb3 0x7 lfsrcfg3 dout 0x8 lfsrcfg1 poly4 0x9 poly3 poly2 0xa poly1 poly0 0xb rescmp3 rescmp2 0xc rescmp1 rescmp0 all registers initialized to 0x00 upon reset, except resx = 0xff, rescmpx = 0xff, and lfsrcfg1 = 0x10). 76 5 43 0 rsvd set_res done cmp_res shift_count3:0
76 www.ubicom.com IP2012 / ip2022 data sheet 5.9.2 lfsrcfg2 register figure 5-23 lfsrcfg2 register ? dout_dout_en ?set to enable dout multiplexer output in source gating for dout node. ? din_dout_en ?set to enable din signal in source gating for dout node. ? fb1_dout_en ?set to enable fb1 signal in source gating for dout node. ? fb2_dout_en ?set to enable fb2 signal in source gating for dout node. ? din_d0_en ?set to enable din signal in source gat- ing for d0 node. ? fb1_d0_en ?set to enable fb1 signal in source gat- ing for d0 node. ? fb2_d0_en ?set to enable fb2 signal in source gat- ing for d0 node. ? d at a_in_polyxor_en ?set to enable din signal in source gating for poly_xor_en node. 5.9.3 lfsrcfg3 register figure 5-24 lfsrcfg3 register ? au t oload_en ?set to enable autoloading datain register when sxrbuf register of corresponding serdes unit is loaded. ? ml_out ?set to shift data out of residue register lsb, and into msb, clear to shift data out of residue register msb, and into lsb. see figure 5-20 for effect on resx mapping. ? ml_in ?set to shift data from datain register msb- rst to din node, clear to shift data lsb- rst. ? hl_trigger ?set to trigger operation start on load- ing datainh register, clear to trigger on datainl. ? fb3_d0_en ?set to enable fb3 signal in source gat- ing for d0 node. ? fb4_d0_en ?set to enable fb4 signal in source gat- ing for d0 node. 5.9.4 datain register the 8-bit datainh and datainl registers together comprise the 16-bit datain register. for lfsr0 and lfsr2, the autoload_en bit in the lfsrcfg3 register can be used to enable automatic loading from serdes1. for lfsr1 and lfsr3, the autoload_en bit in the lfsrcfg3 register can be used to enable automatic loading from serdes2. the hl_trigger bit in the lfsrcfg3 register controls whether loading the d at ainh or datainl register triggers the start of the lfsr operation. the ml_in bit in the lfsrcfg3 register controls whether data is shifted msb- rst or lsb- rst from the datain register to the din node. 5.9.5 dataout register the 8-bit dataouth and dataoutl registers together comprise the 16-bit dataout register. data shifted out of the residue register is shifted lsb- rst into the dataout register. 5.9.6 dout register the dout register controls a 40:1 multiplexer on the residue register outputs. it selects a term which can be used in the source gating for the dout bit stream. 5.9.7 fbx registers the four fbx registers control four 40:1 multiplexers on the residue register outputs. they select feedback terms which can be used in the source gating for the d0, poly_xor_en, and dout bit streams. 5.9.8 polyx registers the ve polyx registers hold the 40-bit polynomial used in the lfsr operation. 5.9.9 resx registers the ve resx registers hold the 40-bit residue used in the lfsr operation. the ml_out bit controls the mapping of the residue register to the resx registers, as shown in 76543210 dout_dout_en din_dout_en fb1_dout_en fb2_dout_en din_d0_en fb1_d0_en fb2_d0_en d at a_in_polyxor_en 76543210 reserved au t oload_en ml_out ml_in hl_trigger fb3_d0_en fb4_d0_en
IP2012 / ip2022 data sheet www.ubicom.com 77 figure 5-20. the residue register can be initialized to all ones by setting the set_res bit in the lfsrcfg1 register. 5.9.10 rescmpx registers the four rescmpx registers hold a 32-bit value for comparison with the contents of the residue register. after an lfsr operation is completed, the cmp_res bit in the lfsrcfg1 register indicates whether the result of the operation matched the 32-bit value. when the ml_out bit in the lfsrcfg3 register is clear, bits 39:8 of the residue register are compared against bits 0:31 of the rescmp register. when ml_out is set, bits 0:31 of the residue register are compared against bits 0:31 of rescmp.
78 www.ubicom.com IP2012 / ip2022 data sheet 5.9.11 lfsr con guration the lfsr units were designed with the following communication protocols in mind: bluetooth, ethernet, homeplug, homepna, homerf, ieee 802.11, and usb. ta b le 5-18 shows the lfsr con gurations used to support these protocols. ta b le 5-18 lfsr con gurations for various protocols protocol subfunction d0 in feedback d out usb crc16 din^d15 din^d15 crc5 din^d4 din^d4 ethernet crc32 din^d31 din^d31 scrambler din^d17^d22 din^d17^d22 descrambler din din^d17^d22 homeplug crc8 din^d7 din^d7 crc16 din^d15 din^d15 scrambler d6^d3 din^d6^d3 homepna crc8 din^d7 din^d7 crc16 din^d15 din^d15 scrambler d17^d22 din^d17^d22 802.11 crc32 (fcs) din^d31 din^d31 crc16 (hec) din^d15 din^d15 data whitening d3^d6 din^d3^d6 crc16 (crc) din^d15 din^d15 scrambler din^d3^d6 din^d3^d6 descrambler din din^d3^d6 home-rf crc din^d31 din^d31 scrambler din din^d3^d8 descrambler din din^d3^d8 bluetooth fec din^d4 din^d4 hec din^d7 din^d7 crc16 din^d15 din^d15 data whitening d6 d6 din^d6 encryption din^d8^d12^d20^d25 d24 din^d12^d16^d24^d31 d24 din^d4^d24^d28^d33 d32 din^d4^d28^d36^d39 d32
IP2012 / ip2022 data sheet www.ubicom.com 79 5.10 parallel slave peripheral (psp) the parallel slave peripheral allows the IP2012 / ip2022 to operate as an 8- or 16-bit slave to an external device, m uch like a memory chip. the ip2022 supports either 8- bit or 16-bit wide bus operation, while the IP2012 is 8-bit wide bus only. alternate functions of port c and port d are used for transferring data, and alternate functions of port b are used for control signals. figure 5-25 shows the connections between an external master and the parallel slave peripheral interface. figure 5-25 parallel slave peripheral to read or write through the parallel slave peripheral interface, the external master asserts the chip select (cs ) signal low. this signal is an alternate function of port pin rb7. the direction of transfer is indicated by the r/w signal, which is an alternate function of port pin rb6. when the r/w signal is high, the master is reading from the slave. when the r/w signal is low, the master is writing to the slave. optionally, a hold signal may be enabled as an alternate function of port pin rb5. assertion of hold indicates to the external master that the parallel slave peripheral interface is not ready to allow the data transfer to complete. the hold signal is driven like an open- collector signal, i.e. low when asserted and high- impedance when not asserted. when the cs signal is not asserted (i.e. the IP2012 / ip2022 is not selected), the hold signal is in high-impedance mode. the hold signal should have an external pullup resistor (r1 = 10k ? is recommended). the cs signal must not be allowed to oat. when cs is asserted, an interrupt is generated and hold (if enabled) is automatically asserted. if the data transfer is a write from the external master, software reads the port c, port d, or both. if the data transfer is a read, software writes the data to the port or ports. finally, if hold is asserted, software releases assertion of hold by writing to the psprdy bit in the pspcfg register. the parallel slave peripheral does not generate interrupts by itself. software is required to enable port pin rb7 (the cs input) as a falling-edge interrupt input for the parallel slave peripheral to function. the cs signal must go high, then back low, for each data transfer. rb6 (the r/w input) m ust also be con gured as an input. the setting in the rbdir register for rb5 (the hold output) is overridden by the programming of the parallel slave peripheral. 5.10.1 pspcfg register the pspcfg register is used to enable the parallel slave pe r ipheral, select which ports are used for data transfer, enable the hold output, and release the hold output when the data transfer is ready to complete. ? pspen2 ?set to enable port d for data transfer, clear to disable. (if this bit is set, the parallel slave periph- eral overrides the rddir register.) ? pspen1 ?set to enable port c for data transfer, clear to disable. (if this bit is set, the parallel slave periph- eral will immediately override the rcdir register.) ? psphen ?set to enable hold output, clear to dis- able. (if this bit is set, the parallel slave peripheral will immediately override bit 5 of the rbdir register.) ? psprdy ?set to release hold . this bit always reads as 0. ? wd ?watchdog time-out bit. set at reset, if reset was triggered by watchdog timer over ow , otherwise cleared. ? bo ?brown-out reset bit. set at reset, if reset was triggered by brown-out voltage level detection, other- wise cleared. external master data hold IP2012 slave 515-033a.eps r/w cs rb7 rb6 rb5 iovdd r1 rc7:0 external master data data hold ip2022 slave r/w cs rb7 rb6 rb5 iovdd r1 rd7:0 rc7:0 765 43210 pspen2 pspen1 psphen psprdy res wd bo ta b le 5-19 pspcfg register
80 www.ubicom.com IP2012 / ip2022 data sheet 5.11 external memory interface (ip2022 only) po rt c and port d can also be used for a parallel interface f or up to 128k bytes of linear-addressed external memory, (not program memory) as shown in figure 5-26. with additional software-based addressing on i/o, up to 2m b ytes is possible. port c implements the high address bits, and port d is multiplexed between data and the low address bits. a level-triggered 8-bit latch (ti part number sn74ac573 or equivalent) is required for demultiplexing. this latch passes the rd7:0 data when le is high, and holds the data when le is low. figure 5-26 external memory interface external memory is accessed as 16-bit words at word- aligned byte addresses 0x800000 to 0x81fffe, as shown in figure 5-27. external 8-bit memory can only be accessed through the current addrx/addrh/addrl pointer using the iread and iwrite instructions. programs cannot execute directly out of external memory, and commands on the isd/isp interface cannot directly access external memory. note: in order to use the external memory interface correctly, rb[4:7], rc[0:7] and rd[0:7] must all be con gured as outputs through their respective port- direction con guration registers. 5.11.1 emcfg register (ip2022 only) refer to section 7.1.4 for eld de nitions and other information about the emcfg register. note: when external memory is enabled (emen = 1), the rddir register value is overridden. psp function will need to be disabled. port b bits 4-7 interrupts need to be disabled. note: wait one cycle after changing addrx bit 7, emcfg bit 7, or addrsel before executing an fread , fwrite , or ferase , or an iread or ireadi . figure 5-27 external memory map software is responsible for inserting a one-instruction delay between changing the address (i.e. the contents of the addrsel, addrx, addrh, or addrl registers) and executing the iread or iwrite instruction, if required by the timing of the external latch. a read cycle to external memory has the timing shown in figure 5-28. write cycle timing is shown in figure 5-29. the timings shown are recommended for 10ns and 12ns srams. all external memory cycles are 16-bit transfers, with the low byte (a0 = 0) followed by the high byte (a0 = 1). the number of system clocks required for one read or write access cycle is programmable to meet the sram timing. figure 5-28 shows a typical sram read access cycle, with emcfg register set to c9h, that is used to access 10ns sram with a 120 mhz system clock. sram gr ade re ects sram access time (taa) in nanoseconds and typically is a last digit of an sram part number. sram has several important parameters which should be taken into account when calculating emcfg register settings (refer to table 5-21). ta b le 5-20 shows maximum capacitance allowed on any sram controller signal line vs . a given sram grade and emcfg setting that provides reliable access.

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# # $ # #% 515-090a.eps program ram reserved 0x000000 70 0x004000 flash program memory 0x01fffe 0x010000 byte address 0x003ffe 0x00fffe reserved 0x020000 external memory 0x800000 0x7ffffe 0x81fffe
IP2012 / ip2022 data sheet www.ubicom.com 81 note: the formulas and tables above assume that the address latch chip propagation delay is < tsys_clk. software is responsible for allowing a memory cycle to complete before reading datah/datal registers by inserting instructions as follows: ? instructions between iread and read of datah = emrdt + 1 ? instructions between iread and read of datal = 2 * (emrdt + 1) ? instructions between consecutive ireads (not in- cluding iread access cycles) =2 * ( emrdt + 1) figure 5-28 sram read cycle (embrt=1; emrdt=2 cycles) ta b le 5-20 emcfg settings ip2022 system clk max load capacitance on le , rd , wr , a0, and rd7:0(pf) tipd (ns) taa (ns) emcfg register setting 120 10 8 12 c9h 120 30 9 12 c9h 120 50 10 10 c9h 160 10 8 10 d2h 160 30 9 12 d2h * ** system clock is the ip2022?s internal clock, and is shown for reference only. setting embrt adds one extra z state cycle on the rd7:0 bus between cycle 7 and cycle 0, and increases the iread cycle time from 8 to 9 cycles. rc7:0 rd7:0 le (rb6) system clock* 515-088f.eps rd (rb5) a0 (rb7) addr16:9 addr8:1 datah datal addr16:9 addr8:1 iread addr stable 01234567801 1st iread 2nd iread th th toe ** taa tohz
82 www.ubicom.com IP2012 / ip2022 data sheet figure 5-29 sram write cycle (emwrt=2 cycles) ta b le 5-21 timing requirements for sram ip2022's timing requirements signal name units note data hold time th 0ns set emrdt and embrt in the emcfg register such that: sram signal description signal name units note output enable to output data toe (emrdt+1)*tsys_clk - tipd ns 1,2 address to output data taa (emrdt+1.5)*tsys_clk - tipd ns 1,2 output disable to output in hi-z tohz (embrt+1)*tsys_clk - 6ns ns 1,2,3 add instruction(s) after any addr change and before the iread or iwrite in software, such that: latch signal description signal name setup time of address before le tsu (# of instructions added + 1) * tsys_clk - 3ns notes: 1. ip2022's rd is connected to the external sram's oe pin. 2. tsys_clk is the period of the ip2022 system clock, and tipd is the propagation delay internally in the ip2022, of the sram control signals (see table 5-20). 3. the ip2022 should not output on rd7:0 before the sram tri-states this bus (set embrt = 1 if bus contention can exist with embrt = 0). * system clock is the ip2022?s internal clock, and is shown for reference only. rc7:0 rd7:0 le (rb6) system clock* 515-089f.eps wr (rb4) a0 (rb7) addr16:9 addr8:1 datah datal addr16:9 addr8:1 iwrite addr stable 0123 4 56701 datah
IP2012 / ip2022 data sheet www.ubicom.com 83 6.0 in-system programming the ip2000 series devices provide a dedicated serial interface for in-system programming (isp) of the ash program memory and con guration block. isp allows designers to incorporate a small connector which can be used to interface to a device programmer for programming or reprogramming the part after it has been soldered to a circuit board. the interface used for in-system programming (isp) and in-system debugging (isd) is compatible with the spi serial interface protocol. whenever possible, a standard connector should be incorporated in the system design for in-system debugging and programming. the recommended connector layout for the isd/isp interface is shown in figure 6-1. the connector is a male 10-pin connector with 100-mil pin spacing, whose pin assignments are listed in table 6-1. the connector is key ed to prevent backward insertion. figure 6-1 isd/isp connector signal levels on the connector are lvttl-compatible. the target system provides the tsck, tsi, trst , and tss signals with 10k ohm pullup resistors. f or more information about the isd/isp interface and the interaction between the debugger/programmer and the target system, see the ip2000 series users manual . ta b le 6-1 connector pin assignments pin name description 1 key key (not a signal) 2 tss t arget slave select ?active-low sig- nal which enables the IP2012 / ip2022 to communicate on the spi bus. con- nect to pin 1 on the IP2012 / ip2022. 3 gnd ground
4 tsck t arget data clock ?serial clock. con- nect to pin 2 on the IP2012 / ip2022. 5 osc t arget clock oscillator ?if the debug- ger/programmer is capable of supply- ing an osc clock for the target system, then this clock must be con- gurable so that it can be disabled to prevent it from interfering with the tar- get system (i.e. the osc clock output is placed in a high-impedance state). 6 reserved reserved 7 trst t arget reset ?the target system may use the trst signal to reset the entire system, to reset only the IP2012 / ip2022, or it may ignore the trst sig- nal. the debugger/programmer may provide a 100-ms system reset signal (trst ) to the target system. if sup- ported, the trst output must be an open-collector driver to accommo- date other sources of reset in the tar- get system. the minimum source requirement for this driver is 6 ma. the debugger/programmer should not detect or be reset by the trst signal being driven low by the target system. there is no requirement that the part be connected to the trst signal, so the debugger/programmer cannot assume that the part has been reset if the target system pulls the trst pin low. 8 tsi t arget serial input ? sampled on the r ising edge of tsck. connect to pin 3 on the IP2012 / ip2022. 9 vdd power. 2.3 - 3.6v (optional) 10 tso t arget serial output ?d ri v en by the IP2012 / ip2022 after the falling edge of tsck. connect to pin 4 on the part. the IP2012 / ip2022 drives this pin only if tss is held low (tso is tristated otherwise). the tso pin is driven low if tss is driven low while the part is in reset; tso will be driven high as soon as the part is out of reset. ta b le 6-1 connector pin assignments (continued) pin name description
84 www.ubicom.com IP2012 / ip2022 data sheet 7.0 memory reference 7.0.1 registers (sorted by address) ta b le 7-1 shows the addresses and reset values of all special-purpose registers in data memory, sorted by their address. ta b le 7-1 register addresses and reset state address name description register status follow- ing reset (power-on, rst, brown-out rst, watchdog rst) 0x001 reserved reserved reserved 0x002 addrsel selector for current external(ip2022 only)/program memory addrx/addrh/addrl 0000 0000 0x003 addrx external(ip2022 only)/program memory pointer (bits 23:16) 0000 0000 0x004 iph indirect data ram pointer (high byte) 0000 0000 0x005 ipl indirect data ram pointer (low byte, see section 4.1) 0000 0000 0x006 sph data ram stack pointer (high byte) 0000 0000 0x007 spl data ram stack pointer (low byte, see section 4.1) 0000 0000 0x008 pch current pc (program counter) bits 15:8 (read-only) 1111 1111 0x009 pcl virtual register for direct pc modi cation 1111 0000 0x00a wreg w (working) register 0000 0000 0x00b status status register 1110 0000 0x00c dph data pointer (high byte) 0000 0000 0x00d dpl data pointer (low byte, see section 4.1) 0000 0000 0x00e spdreg current speed (read-only, see section 3.5) 1001 0011 0x00f mulh multiply result (high byte) 0000 0000 0x010 addrh external(ip2022 only)/program memory address (bits 15:8) 0000 0000 0x011 addrl external(ip2022 only)/program memory address (bits 7:0, see section 5.11) 0000 0000 0x012 d ata h external(ip2022 only)/program memory data (high b yte) 0000 0000 0x013 d ata l external(ip2022 only)/program memory data (low b yte) 0000 0000 0x014 intvech interrupt vector (high byte) 0000 0000 0x015 intvecl interrupt vector (low byte) 0000 0000 0x016 intspd interrupt speed register 0000 0000 0x017 intf po rt b interrupt ags unde ned 0x018 inte po rt b interrupt enable bits 0000 0000 0x019 inted po rt b interrupt edge select bits 0000 0000
IP2012 / ip2022 data sheet www.ubicom.com 85 0x01a fcfg flash con guration register 0000 0000 0x01b tctrl timer 1/2 common control register 0000 0000 0x01c xcfg extended con guration (bit 0 is read-only) 0000 000x (see section 7.1.26 for fbusy)) 0x01d emcfg external memory con guration register (ip2022 only) 0000 0000 0x01e ipch interrupt return address (high byte) 0000 0000 0x01f ipcl interrupt return address (low byte) 0000 0000 0x020 rain data on port a pins n/a 0x021 raout po rt a output latch 0000 0000 0x022 radir po rt a direction register 1111 1111 0x023 lfsrh lfsr data register (high byte) 0000 0000 0x024 rbin data on port b pins n/a 0x025 rbout po rt b output latch 0000 0000 0x026 rbdir po rt b direction register 1111 1111 0x027 lfsrl lfsr data register (low byte) 0000 0000 0x028 rcin data on port c pins n/a 0x029 rcout po rt c output latch 0000 0000 0x02a rcdir po rt c direction register 1111 1111 0x02b lfsra lfsr address register 0000 0000 0x02c rdin data on port d pins n/a 0x02d rdout po rt d output latch 0000 0000 0x02e rddir po rt d direction register 1111 1111 0x02f reserved reserved reserved 0x030 rein data on port e pins n/a 0x031 reout po rt e output latch 0000 0000 0x032 redir po rt e direction register 1111 1111 0x033 reserved reserved reserved 0x034 rfin data on port f pins n/a 0x035 rfout po rt f output latch 0000 0000 0x036 rfdir po rt f direction register 1111 1111 0x037 reserved reserved reserved 0x038 reserved reserved reserved 0x039 rgout po rt g output latch 0000 0000 0x03a rgdir po rt g direction register 1111 1111 ta b le 7-1 register addresses and reset state (continued) address name description register status follow- ing reset (power-on, rst, brown-out rst, watchdog rst)
86 www.ubicom.com IP2012 / ip2022 data sheet 0x03b reserved reserved reserved 0x03c reserved reserved reserved 0x03d reserved reserved reserved 0x03e reserved reserved reserved 0x03f reserved reserved reserved 0x040 r ttmr real-time timer value 0000 0000 0x041 r tcfg real-time timer con guration register 0000 0000 0x042 t0tmr timer 0 value 0000 0000 0x043 t0cfg timer 0 con guration register 0000 0000 0x044 t1cnth timer 1 counter register high (read only) 0000 0000 0x045 t1cntl timer 1 counter register low (read only) 0000 0000 0x046 t1cap1h timer 1 capture 1 register high (read only) 0000 0000 0x047 t1cap1l timer 1 capture 1 register low (read only) 0000 0000 0x048 t1cap2h/t1cmp2h timer 1 capture 2/compare 2 register high 0000 0000 0x049 t1cap2l/t1cmp2l timer 1 capture 2/compare 2 register low 0000 0000 0x04a t1cmp1h timer 1 compare 1 register high 0000 0000 0x04b t1cmp1l timer 1 compare 1 register low 0000 0000 0x04c t1cfg1h timer 1 con guration register 1 high 0000 0000 0x04d t1cfg1l timer 1 con guration register 1 low 0000 0000 0x04e t1cfg2h timer 1 con guration register 2 high 0000 0000 0x04f t1cfg2l timer 1 con guration register 2 low 0000 0000 0x050 adch adc value (high) (read only) 0000 0000 0x051 adcl adc value (low) (read only) 0000 0000 0x052 adccfg adc con guration register 0000 0000 0x053 adctmr adc timer register 0000 0000 0x054 t2cnth timer 2 counter register high (read only) 0000 0000 0x055 t2cntl timer 2 counter register low (read only) 0000 0000 0x056 t2cap1h timer 2 capture 1 register high (read only) 0000 0000 0x057 t2cap1l timer 2 capture 1 register low (read only) 0000 0000 0x058 t2cap2h/t2cmp2h timer 2 capture 2/compare 2 register high 0000 0000 0x059 t2cap2l/t2cmp2l timer 2 capture 2/compare 2 register low 0000 0000 0x05a t2cmp1h timer 2 compare 1 register high 0000 0000 0x05b t2cmp1l timer 2 compare 1 register low 0000 0000 0x05c t2cfg1h timer 2 con guration register 1 high 0000 0000 0x05d t2cfg1l timer 2 con guration register 1 low 0000 0000 ta b le 7-1 register addresses and reset state (continued) address name description register status follow- ing reset (power-on, rst, brown-out rst, watchdog rst)
IP2012 / ip2022 data sheet www.ubicom.com 87 0x05e t2cfg2h timer 2 con guration register 2 high 0000 0000 0x05f t2cfg2l timer 2 con guration register 2 low 0000 0000 0x060 s1tmrh serdes 1 clock timer register (high bits) 0000 0000 0x061 s1tmrl serdes 1 clock timer register (low bits) 0000 0000 0x062 s1tbufh serdes 1 transmit buffer (high bits) unde ned 0x063 s1tbufl serdes 1 transmit buffer (low bits) unde ned 0x064 s1tcfg serdes 1 transmit con guration 0000 0000 0x065 s1rcnt serdes 1 received bit count (actual) (read-only) 0000 0000 0x066 s1rbufh serdes 1 receive buffer (high bits) (read-only) unde ned 0x067 s1rbufl serdes 1 receive buffer (low bits) (read-only) unde ned 0x068 s1rcfg serdes 1 receive con guration 0000 0000 0x069 s1rsync serdes 1 receive bit sync pattern 0000 0000 0x06a s1intf serdes 1 status/interrupt ags 0000 0000 0x06b s1inte serdes 1 interrupt enable bits 0000 0000 0x06c s1mode serdes 1 serial mode/clock select register 0000 0000 0x06d s1smask serdes 1 receive sync mask 0000 0000 0x06e pspcfg pa r allel slave peripheral con guration register 0000 00xx (see section 7.1.8 for bo, wd) 0x06f cmpcfg comparator con guration register 0000 000x (see section 7.1.3) 0x070 s2tmrh serdes 2 clock timer register (high bits) (ip2022 only) 0000 0000 0x071 s2tmrl serdes 2 clock timer register (low bits) (ip2022 only) 0000 0000 0x072 s2tbufh serdes 2 transmit buffer (high bits) (ip2022 only) unde ned 0x073 s2tbufl serdes 2 transmit buffer (low bits) (ip2022 only) unde ned 0x074 s2tcfg serdes 2 transmit con guration (ip2022 only) 0000 0000 0x075 s2rcnt serdes 2 received bit count (actual) (read-only) (ip2022 only) 0000 0000 0x076 s2rbufh serdes 2 receive buffer (high bits) (read-only) (ip2022 only) unde ned 0x077 s2rbufl serdes 2 receive buffer (low bits) (read-only) (ip2022 only) unde ned 0x078 s2rcfg serdes 2 receive con guration (ip2022 only) 0000 0000 0x079 s2rsync serdes 2 receive bit sync pattern (ip2022 only) 0000 0000 0x07a s2intf serdes 2 status/interrupt ags (ip2022 only) 0000 0000 0x07b s2inte serdes 2 interrupt enable bits (ip2022 only) 0000 0000 ta b le 7-1 register addresses and reset state (continued) address name description register status follow- ing reset (power-on, rst, brown-out rst, watchdog rst)
88 www.ubicom.com IP2012 / ip2022 data sheet 7.0.2 program memory ta b le 7-2 shows the addresses and reset values of all program memory. 0x07c s2mode serdes 2 serial mode/clock select register (ip2022 only) 0000 0000 0x07d s2smask serdes 2 receive sync mask (ip2022 only) 0000 0000 0x07e callh t op of call stack (high 8 bits) 1111 1111 0x07f calll t op of call stack (low 8 bits) 1111 1111 0x080 to 0x0ff directly addressable general-purpose (global) reg- isters unde ned after power-on or brown-out reset, unchanged after rst or w atchdog timer reset 0x100 to 0xfff data memory ram unde ned after power-on or brown-out reset, unchanged after rst or w atchdog timer reset ta b le 7-1 register addresses and reset state (continued) address name description register status follow- ing reset (power-on, rst, brown-out rst, watchdog rst) ta b le 7-2 program memory addresses address description status following reset (power-on, rst, brown-out rst, watchdog rst) 0x0000 to 0x1fff (word addresses) program memory ram unde ned after power-on or brown- out reset, unchanged after rst or w atchdog timer reset 0x8000 to 0xffff (word addresses) program memory flash. unchanged after power-on, brown-out reset, rst or watchdog timer reset (changes only during isp program- ming, and during ash self-program- ming) 0x10000 to 0x1003f (word addresses) flash con guration block (see section 3.10). flash is factory programmed to: unchanged after power-on, brown-out reset, rst or watchdog timer reset (changes only during isp program- ming, and during ash self-program- ming) wo rd address $ 10000 $ 10001 $ 10004 fuse0 fuse1 trim0 = 1000 = fff7 = fbfe
IP2012 / ip2022 data sheet www.ubicom.com 89 7.1 register bit de nitions f or those registers which have special functions assigned to bits or elds within the register, the de nition of those bits and elds is described below. the registers are presented alphabetically. 7.1.1 adccfg register a/d converter con guration. 7.1.2 adctmr register the adctmr register is used to specify the number of system clock cycles required for a delay of 1736 ns, which is used to provide the 1.152mhz (48 khz 24) clock period reference clock for the a/d converter. 7.1.3 cmpcfg register comparator con guration. 765432 0 adcref adcjst rsrvd. adcgo adcs2:0 name description adcref a/d converter reference voltage select 0 = avdd is the reference voltage 1 = rg3 port pin is used to receive an external reference voltage adcjst a/d converter result justi cation mode select 00 = right justi ed 01 = signed 10 = left justi ed 11 = reserved adcgo a/d converter go/done bit 0 = when the last conversion has completed, this bit reads as 0. 1 = write 1 to begin a new conver- sion. while the conversion is in progress, this bit reads as 1. adcs2:0 a/d converter input channel select 000 = port pin rg0 001 = port pin rg1 010 = port pin rg2 011 = port pin rg3 100 = port pin rg4 101 = port pin rg5 110 = port pin rg6 111 = port pin rg7 76543210 cmpen cmpoe cmphys reserved cmpres name description cmpen comparator enable bit 0 = comparator disabled 1 = comparator enabled cmpoe comparator output enable bit 0 = comparator output disabled. 1 = comparator output enabled on port pin rg0. cmphys comparator hysteresis enable bit 0 = hysteresis disabled 1 = hysteresis enabled cmpres comparator result (read-only) 0 = rg2 voltage > rg1 1 = rg1 voltage > rg2
90 www.ubicom.com IP2012 / ip2022 data sheet 7.1.4 emcfg register (ip2022 only) external memory interface con guration. (reserved in IP2012; value 0x00.) 765 3 20 emen embrt emwrt2:0 emrdt2:0 name description emen enable external memory interface 0 = port c, port d and rb7:4 avail- able for general-purpose i/o 1 = port c, port d and rb7:4 used f or external memory interface embrt enable bus release wait state 0 = no wait state one wait state cycle added to iread and iwrite after read of d at al and before addr8:1 is put on rd7:0 bus 1 = emwrt2:0 wr pulse width, in system clock cycles 000 = 1 100 = 5 001 = 2 101 = 6 010 = 3 110 = 7 011 = 4 111 = 8 emrdt2:0 rd pulse width, in system clock cycles 000 = 1 100 = 5 001 = 2 101 = 6 010 = 3 110 = 7 011 = 4 111 = 8
IP2012 / ip2022 data sheet www.ubicom.com 91 7.1.5 fcfg register flash con guration. 76543210 frdts1:0 frdtc1:0 fwrt3:0 name description frdts1:0 the core clock frequency is automatically reduced (if necessary) when executing out of ash memory to prevent the ash memory access time from being too short. the frdts1:0 bits specify the minimum n umber of system clock cycles required for instruction execution from ash memory. the actual execu- tion speed from ash memory will be the slower of the speed indicated in the spdreg register and the speed speci ed by the frdts1:0 bits. the 11 setting can always be used, but it may cause slower ash operation than necessary. set to this: if system clock frequency (mhz) is system clock cycles for each flash instruction cycle 120 mhz part 160 mhz part 00 0?40 0?53.3 1 cycle 01 40?80 53.3?106.7 2 cycles 10 80?120 106.7?160 3 cycles 11 reserved reserved 4 cycles note flash instruction execution = 25ns minimum (18.75ns for 160mhz part) frdtc1:0 to prevent the ash memory access time from being too short, it is necessary to specify the number of cpu core cycles between reading the ash memory using an fread instruction (or an iread or ireadi instruction while executing from ram to read ash) and the time that datah and datal are written by the IP2012 / ip2022. because the cpu core is subject to changes in speed, the value pro- gr ammed in these bits should be appropriate for the fastest speed that might be used (typically, the f aster of the main line code and the interrupt service routine). the frdtc1:0 bits specify the number of cpu core clock cycles required for ash read access. even with this con gured, enough cycles must be ex ecuted after the ash read instruction and before reading datah or datal to account for the mini- m um ash access time. set to this: if cpu core frequency (mhz) is core clock cycles for each flash read cycle 120 mhz part 160 mhz part 00 0?40 0?53.3 1 cycle 01 40?80 53.3?106.7 2 cycles 10 80?120 106.7?160 3 cycles 11 reserved reserved 4 cycles note fread / iread / ireadi of ash= 25ns minimum (18.75ns for 160mhz part) fwrt3:0 the ash memory ferase , fwrite and isp ash write, ash block erase, or ash bulk erase timing is derived from the cpu core clock through a programmable divider. the fwrt3:0 bits specify the divi- sor. the time base must be 1 to 2 microseconds. below 1 microsecond, the ash memory will be under- programmed, and data retention is not guaranteed. above 2 microseconds, the ash memory will be ov erprogrammed, and reliability is not guaranteed. set to this: if cpu core frequency is: fwrt frequency divisor 0000 1?2 mhz 2 0001 2?3 mhz 3 0010 3?4 mhz 4 0011 4?6 mhz 6
92 www.ubicom.com IP2012 / ip2022 data sheet 7.1.6 intspd register con guration of clock and pll settings to be used during an interrupt service routine. intspd is copied to spdreg when an interrupt occurs. see table 3-5 for reti options. 0100 6?8 mhz 8 0101 8?12 mhz 12 0110 12?16 mhz 16 0111 16?24 mhz 24 1000 24?32 mhz 32 1001 32?48 mhz 48 1010 48?64 mhz 64 1011 64?96 mhz 96 1100 96?128 mhz 128 1101 128?160 mhz 192 1110 reserved 256 1111 reserved 384 note: if fcfg & osc1 are optimal: fwrite = 42us ferase = 20ms, because fpert in trim0 should be 0 name description 76543 0 pll osc clk1:0 cdiv3:0 name description pll run-time control of pll clock multiplier oper- ation. if the pll is not required, power con- sumption can be reduced by disabling it. 0 = pll clock multiplier enabled 1 = pll clock multiplier disabled osc run-time control of osc oscillator operation. if the crystal oscillator is not required, power consumption can be reduced by disabling it (stops osc oscillator and blocks propaga- tion of osc1 external clock input). 0 = osc oscillator enabled 1 = osc oscillator disabled clk1:0 selects the system clock source. 00 = pll clock multiplier. do not use if an interrupt can awaken the part from sleep (can use a speed instruction in the isr instead). 01 = osc oscillator/external clock on osc1 input 10 = rtclk oscillator/external clock on rtclk1 input 11 = system clock disabled (off) note: if the osc crystal driver is stopped (spdreg bit 6 = 1) and port b or real time timer interrupts are enabled, then intspd bits 5 and 4 must not both be 0, because the crystal startup time plus pll startup time may be greater than wudp2:0 (see figure 3-16). cdiv3:0 selects the system clock divisor. 0000 = 1 1000 = 12 0001 = 2 1001 = 16 0010 = 3 1010 = 24 0011 = 4 1011 = 32 0100 = 5 1100 = 48 0101 = 6 1101 = 64 0110 = 8 1110 = 128 0111 = 10 1111 = system clock disabled (off) name description
IP2012 / ip2022 data sheet www.ubicom.com 93 7.1.7 lfsra register linear feedback shift register con guration. 7.1.8 pspcfg register pa r allel slave peripheral con guration. 7430 unit3:0 index3:0 name description unit3:0 lfsr unit number (only 0, 1, 2, and 3 are v alid) index3:0 index to the lfsr register being accessed (see table 5-17) 765 4310 pspen2 pspen1 psphen psprdy res wd bo name description pspen2 port d enable bit (ip2022 only) 0 = port d is available for general- purpose i/o 1 = port d is con gured for the pa r allel slave peripheral inter- f ace pspen1 port c enable bit 0 = port c is available for general- purpose i/o 1 = port c is con gured for the pa r allel slave peripheral inter- f ace psphen hold output enable bit 0 = hold output disabled. port pin rb5 available for general-pur- pose i/o. 1 = hold output enabled on port pin rb5. psprdy ready bit 0 = this bit always reads as zero. 1 = write 1 to release hold when the IP2012 / ip2022 is ready to allow the data transfer to com- plete. wd watchdog time-out bit. if using the watch- dog feature, set this bit before the rst cwdt instruction. then this bit is not cleared by a watchdog reset, but is cleared by all other reset sources. how- ev er, if wudx in fuse0 is more than 70ms longer than the watchdog timeout period in fuse1, a power-on reset or a brown-out reset may set this bit. (do not use this bit if wudx is more than 70ms longer than the watchdog timeout period). bo brown-out reset bit. set at reset, if reset w as triggered by brown-out voltage level detection, otherwise cleared
94 www.ubicom.com IP2012 / ip2022 data sheet 7.1.9 rtcfg register real-time timer con guration. 76 3210 r ten rtps3:0 rtss rtie rtif name description r ten real-time timer enable bit 0 = real-time timer disabled 0 = real-time timer enabled r tps3:0 real-time timer prescaler divisor 0000 = 1 1000 = 256 0001 = 2 1001 = 512 0010 = 4 1010 = 1024 0011 = 8 1011 = 2048 0100 = 16 1100 = 4096 0101 = 32 1101 = 8192 0110 = 64 1110 = 16384 0111 = 128 1111 = 32768 r tss real-time timer clock source select 0 = external osc clock 1 = external rtclk clock r tie real-time timer interrupt enable bit 0 = real-time timer interrupt dis- abled 1 = real-time timer interrupt enabled r tif real-time timer interrupt ag 0 = no timer over ow has occurred since this bit was last cleared 1 = timer over ow has occurred. this bit goes high two cycles after the actual over ow occurs.
IP2012 / ip2022 data sheet www.ubicom.com 95 7.1.10 sxinte/sxintf register indicates the serdes conditions that may be enabled as interrupts. the sxinte register has the same format as the sxintf register. for each condition indicated by a ag in the sxintf register, setting the corresponding bit in the sxinte register enables the interrupt for that condition. 76543210 rxerror rxeop synd txbe txeop sxlinkpulse rxbf rxxcrs name description rxerror receive error interrupt ag 10base-t mode: manchester encod- ing data phase error usb mode: bit unstuf ng error (1111111 received) 0 = receive error has not been detected since this bit was last cleared 1 = receive error has been detected rxeop end-of-packet detection interrupt ag 10base-t and usb modes: end-of- packet detected gpsi mode: rxen deasserted spi mode: set on rising edge. 0 = end-of-packet has not been detected since this bit was last cleared 1 = end-of-packet has been detected synd synchronization pattern detection interrupt ag (10base-t and usb modes only) 0 = synchronization pattern has not been detected since this bit was last cleared 1 = synchronization pattern has been detected txbe transmit buffer empty interrupt ag 0 = transmit buffer has not been empty since this bit was last cleared 1 = transmit buffer has been empty txeop transmit underrun. this bit is set when the previous data in the transmit b uffer register (sxtxbuf) has been transmitted and no new data has been loaded in the register. in usb and 10base-t modes, this causes an eop condition to be generated. 0 = transmit underrun has not occurred since this bit was last cleared 1 = transmit underrun has occurred sxlinkpulse set after a link pulse of 60 to 200 ns duration is detected in ethernet mode. also known as txidle in usb mode. 0 = 10base-t mode: no link pulse has been detected since this bit w as last cleared usb mode: serdes is trans- mitting 1 = 10base-t mode: link pulse detected usb mode: serdes is not transmitting rxbf receive buffer full interrupt ag 0 = receive buffer has not been full since this bit was last cleared 1 = receive buffer has been full rxxcrs set while the carrier is sensed. 10bt mode: clear to 0 0 = usb mode: rxbusy is detected - serdes is receiving 1 = usb mode: rxbusy is not detected - serdes is not receiving name description
96 www.ubicom.com IP2012 / ip2022 data sheet 7.1.11 sxmode register serdes protocol mode con guration. 7.1.12 sxrcfg register serdes rx shift count, usb sync detect and data polarity con guration. 76543210 rev prs2:0 subm1:0 clks1:0 name description rev read-only as ?1? in latest revision. refer to ip2022 silicon errata sheet. prs2:0 protocol select (see table 5-3). all other encodings are reserved. 000 = disabled 001 = 10base-t 010 = usb bus 011 = uart 101 = spi 110 = gpsi subm1:0 submode select usb mode: 01 = low-speed usb interface 10 = high-speed usb interface spi mode: 00 = positive clock polarity, receive on rising edge, transmit on fall- ing edge 01 = positive clock polarity, receive on falling edge, transmit on ris- ing edge 10 = negative clock polarity, receive on falling edge, transmit on ris- ing edge 11 = negative clock polarity, receive on rising edge, transmit on fall- ing edge gpsi mode: 00 = receive on rising edge, trans- mit on falling edge 01 = receive on falling edge, trans- mit on falling edge 10 = receive on rising edge, trans- mit on rising edge 11 = receive on falling edge, trans- mit on rising edge clks1:0 clock source select (see figure 5-8). 00 = clock disabled 01 = sxclk input 10 = osc clock oscillator 11 = post-pll clock note: when switching clks1:0 to 10, a delay is needed before reliable writes to serdes registers can be made. the required delay, in number of core instruc- tions, is (core clock frequency / new ser- des clock frequency) x 2. 7654 0 massel syncdeten rporev rxscnt4:0 name description massel 10base-t mode: 0 = normal polarity detected 1 = reverse polarity detected gpsi or spi mode: 0 = slave mode 1 = master mode syncdeten synchronization byte detection enable (usb mode only) 0 = synchronization byte detec- tion enabled 1 = synchronization byte detec- tion disabled rporev receive data polarity reversal select 0 = data polarity uninverted 1 = data polarity inverted rxscnt4:0 receive shift count, speci es number of bits to receive name description
IP2012 / ip2022 data sheet www.ubicom.com 97 7.1.13 sxrcnt register serdes rx activity con guration. 7.1.14 sxrsync register serdes sync pattern con guration. 7654 0 bitorder rxcrsed rxcrs rxacnt4:0 name description bitorder bit order for transmit and receive 0 = lsb rst 1 = msb rst rxcrsed not used for 10baset mode. for gpsi slave mode: 0 = disable txbusy input 1 = enable txbusy input rxcrs carrier sense status: current state of carrier rxacnt4:0 receive shift count, actual number of bits received (read-only). excep- tions occur during the last transfer: rxacnt = 0 if bit count is less than 8 rxacnt = 8 if bit count is g reater than or equal to 8, but less than 16 rxacnt = 16 if bit count is g reater than or equal to 16 and the rxscnt4:0 eld in the sxrcfg register is 16 7210 syncpat7:2 squelchen dribbiten name description syncpat7:2 synchronization pattern, bits 7:2 (usb mode only) squelchen usb mode: synchronization pattern, bit 1 10base-t mode: 0 = squelch disabled 1 = squelch enabled all other modes: 0 dribbiten usb mode: synchronization pattern, bit 0 10base-t mode: 0 = hardware handles dribble bit 1 = software is responsible for han- dling dribble bit
98 www.ubicom.com IP2012 / ip2022 data sheet 7.1.15 sxsmask register serdes sync-pattern con guration. 10base-t mode: usb mode: 7.1.16 sxtcfg register serdes tx shift count con guration. 76 3 210 resrvd. preamcnt3:0 resrvd. contpair resrvd. 70 mask7:0 name description preamcnt3:0 preamble pair count (10base-t mode only). all other encodings are reserved. 0000 = 24 pairs 0001 = 20 pairs 0010 = 16 pairs 0011 = 12 pairs 0100 = 8 pairs 0101 = 4 pairs contpair con gures the detection of consecu- tive pairs of ?10? for sync detection. 0 = sync detected if 6 "10" pairs + "11?. 1 = use preamcnt for num- ber of "10" pairs mask7:0 mask bits for sxrsync (usb mode only) 0 = ignore corresponding bit in sxrsync 1 = use corresponding bit in search pattern for synchro- nization byte 7654 0 globen lpback tporev txscnt4:0 name description globen global enable bit 0 = disable serdes output 1 = enable serdes output (must use for tx). if enabling serdes1, the reout port data are overridden by serdes1 out- puts. if enabling serdes2 (ip2022 only), the rfout port data are overridden by serdes2 outputs. lpback loopback enable bit 0 = normal operation 1 = output is driven into input tporev transmit data polarity reversal select (uart mode only) 0 = data polarity uninverted 1 = data polarity inverted txscnt4:0 transmit shift count, speci es number of bits to transmit
IP2012 / ip2022 data sheet www.ubicom.com 99 7.1.17 sxtmrh/sxtmrl register used to specify the divide value for the osc clock, post- pll clock or sxclk input (speci ed in the sxmode register bits clks1:0, section 7.1.11) to generate the serdes clock. the effective divide value = {sxtmrh, sxtmrl} + 1, except, in the case of spi and gpsi master, the effective divide value = {(sxtmrh/sxtmrl) + 1} x 2. 7.1.18 spdreg register status of clock and pll settings during run-time. note: this is a read-only register, use speed instruction to change settings. 76543 0 pll osc clk1:0 cdiv3:0 name description pll run-time control of pll clock multiplier operation. if the pll is not required, power consumption can be reduced by disabling it, but a wudp delay is required to start it again (controlled in fuse0). 0 = pll clock multiplier on 1 = pll clock multiplier off osc run-time control of osc oscillator opera- tion. if the osc clock is not required, power consumption can be reduced by disabling it (stops osc crystal oscillator and blocks propagation of osc1 external clock input). 0 = osc oscillator enabled 1 = osc oscillator disabled clk1:0 selects the system clock source. 00 = pll clock multiplier 01 = osc oscillator/external clock on osc1 input 10 = rtclk oscillator/external clock on rtclk1 input 11 = system clock disabled (off) cdiv3:0 selects the divisor which divides the sys- tem clock to give the core clock. 0000 = 1 0001 = 2 0010 = 3 0011 = 4 0100 = 5 0101 = 6 0110 = 8 0111 = 10 1000 = 12 1001 = 16 1010 = 24 1011 = 32 1100 = 48 1101 = 64 1110 = 128 1111 = system clock disabled (off) name description
100 www.ubicom.com IP2012 / ip2022 data sheet 7.1.19 status register condition ags for the results of arithmetic and logical operations, the page bits, and bits which indicate the skipping state of the core and control of continuation skip after return from interrupt. 7 543210 p a2:0 sar ssf z dc c name description p a2:0 program memory page select bits (read only). used to extend the 13-bit address encoded in jump and call instructions (these 3 bits are written to the upper 3 bits of the program counter when a jump or call occurs). modi ed using the page instruction. sar skip after return bit. indicates if the core should be in the skipping/not state after the completion of a return instruction ( ret , retnp , or retw instructions, but not reti ). the return instruction will also clear the sar bit to ensure correct behav- ior after the dynamic jump. 0 = the core should not be in a skipping state upon comple- tion of the return. 1 = the core should be in a skip- ping state upon completion of the return. ssf shadowed skipping/not state flag. gives the isr the ability to know if the interrupt occurred immediately following a skip instruction. the software can choose either to clear the ssf ag in the isr or to make the rst instruction of the mainline context switching code a nop to ush out the skip state. 0 = the core was not in a skipping state when interrupted. 1 = the core was in a skipping state when interrupted. z zero bit. affected by most logical, arith- metic, and data movement instructions (refer to ?flags affected? column in table 4-2 through table 4-7). set if the result w as zero, otherwise cleared. 0 = result of last alu operation w as non-zero. 1 = result of last alu operation w as zero. dc digit carry bit. after addition, set if carry from bit 3 occurred, otherwise cleared. after subtraction, cleared if borrow from bit 3 occurred, otherwise set. 0 = last addition did not generate carry out of bit 3, or last sub- traction generated borrow out of bit 3. 1 = last addition generated carry out of bit 3, or last subtraction did not generate borrow out of bit 3. c carry bit. after addition, set if carry from bit 7 of the result occurred, otherwise cleared. after subtraction, cleared if bor- row from bit 7 of the result occurred, oth- erwise set. after rotate ( rr or rl ) instructions, loaded with the lsb or msb of the operand, respectively. 0 = last addition did not generate carry out of bit 7, last subtrac- tion generated borrow out of bit 7, or last rotate loaded a 0. 1 = last addition generated carry out of bit 7, last subtraction did not generate borrow out of bit 7, or last rotate loaded a 1. name description
IP2012 / ip2022 data sheet www.ubicom.com 101 7.1.20 t0cfg register timer 0 con guration. 7.1.21 txcfg1h register timer 1 and 2 con guration. 76 3 2 10 t0en t0ps3:0 rsrvd. t0ie t0if name description t0en enables timer 0 0 = timer 0 disabled 1 = timer 0 enabled t0ps3:0 speci es timer 0 prescaler divisor 0000 = 1 0001 = 2 0010 = 4 0011 = 8 0100 = 16 0101 = 32 0110 = 64 0111 = 128 1000 = 256 1001 to 1111 = reserved t0ie timer 0 interrupt enable bit 0 = timer 0 interrupt disabled 1 = timer 0 interrupt enabled t0if timer 0 interrupt ag 0 = no timer over ow has occurred since this bit was last cleared 1 = timer over ow has occurred 76543210 ofie cap2ie cmp2ie cap1ie cmp1ie ofif cap2if cmp2if cap1if cmp1if name description ofie timer over ow interrupt enable bit 0 = over ow interrupt disabled 1 = over ow interrupt enabled cap2ie or pwm mode: compare 2 interrupt enable bit cmp2ie capture/compare mode: capture 2 inter- r upt enable bit 0 = capture/compare 2 interrupt disabled 1 = capture/compare 2 interrupt enabled cap1ie capture 1 interrupt enable bit 0 = capture 1 interrupt disabled 1 = capture 1 interrupt enabled cmp1ie compare 1 interrupt enable bit 0 = compare 1 interrupt disabled 1 = compare 1 interrupt enabled ofif timer over ow interrupt ag 0 = no timer over ow has occurred since this bit was last cleared 1 = timer over ow has occurred cap2if or pwm mode: compare 2 interrupt ag (i.e. timer value matched txcmp2 value) cmp2if capture/compare mode: capture 2 ag (i.e. txcpi2 input triggered) 0 = no capture/compare 2 event has occurred since this bit was last cleared 1 = capture/compare 2 event has occurred cap1if capture 1 interrupt ag 0 = no capture 1 event has occurred since this bit was last cleared 1 = capture 1 event has occurred cmp1if compare 1 interrupt ag 0 = no compare 1 event has occurred since this bit was last cleared 1 = compare 1 event has occurred name description
102 www.ubicom.com IP2012 / ip2022 data sheet 7.1.22 txcfg2h register timer 1 and 2 con guration. 7.1.23 txcfg1l register timer 1 and 2 con guration. 76543 0 0000 ps3:0 name description ps3:0 timer prescaler divisor 0000 = 1 1000 = 256 0001 = 2 1001 = 512 0010 = 4 1010 = 1024 0011 = 8 1011 = 2048 0100 = 16 1100 = 4096 0101 = 32 1101 = 8192 0110 = 64 1110 = 16384 0111 = 128 1111 = 32768 76543210 mode oen eclken cpi2en cpi1en eclkedg cap1rst tmren name description mode timer mode select 0 = pwm/timer mode 1 = capture/compare mode oen txout enable bit 0 = txout disabled. port pin avail- able for general-purpose i/o. 1 = txout enabled. port pin must be con gured for output in cor- responding rxdir register bit. output is on ra3 for t1, rb3 f or t2 eclken txclk enable bit 0 = txclk disabled. port pin avail- able for general-purpose i/o. 1 = txclk enabled as clock source for timer. enabling this bit does not make any other restrictions on the use of the txclk port pin for general-pur- pose i/o. cpi2en txcpi2 enable bit 0 = system clock enabled as clock source for timer. txcpi2 port pin available for general-pur- pose i/o. 1 = txclk enabled as clock source for timer. enabling this bit does not make any other restrictions on the use of the port pin for general-purpose i/o. cpi1en txcpi1 enable bit 0 = capture 1 input disabled. txcpi1 port pin available for general-purpose i/o. 1 = txcpi1 enabled as capture 1 input. enabling this bit does not make any other restrictions on the use of the port pin for gen- eral-purpose i/o. eclkedg txclk edge sensitivity select. (this bit is ignored if the eclken bit is clear.) 0 = txclk increments timer on ris- ing edge 1 = txclk increments timer on fall- ing edge cap1rst reset timer on capture 1 event enable bit 0 = timer value unchanged by occurrence of a capture 1 ev ent 1 = timer value cleared by occur- rence of a capture 1 event tmren timer enable bit 0 = timer disabled. timer clock source shut off to reduce power consumption. 1 = timer enabled name description
IP2012 / ip2022 data sheet www.ubicom.com 103 7.1.24 txcfg2l register timer 1 and 2 con guration. 76 54 3210 reserved t outset t outclr cpi2cpi1 cpi2edg1:0 cpi1edg1:0 name description t outset override bit to set the txout output. this bit always reads as zero. 0 = writing 0 to this bit has no effect 1 = writing 1 to this bit forces the txout signal high t outclr override bit to clear the txout output. this bit always reads as zero. 0 = writing 0 to this bit has no effect 1 = writing 1 to this bit forces the txout signal low cpi2cpi1 internally connect the txcpi2 input to the txcpi1 input. this makes the txcpi2 port pin available for general- purpose i/o. 0 = no internal connection between txcpi1 and txcpi2 1 = txcpi1 and txcpi2 internally connected cpi2edg1:0 txcpi2 edge sensitivity select 00 = falling edge on txcpi2 rec- ognized as capture 2 event 01 = rising edge on txcpi2 rec- ognized as capture 2 event 10 = any falling or rising edge on txcpi2 recognized as cap- ture 2 event 11 = any falling or rising edge on txcpi2 recognized as cap- ture 2 event cpi1edg1:0 txcpi1 edge sensitivity select 00 = falling edge on txcpi1 rec- ognized as capture 1 event 01 = rising edge on txcpi1 rec- ognized as capture 1 event 10 = any falling or rising edge on txcpi1 recognized as cap- ture 1 event 11 = any falling or rising edge on txcpi1 recognized as cap- ture 1 event name description
104 www.ubicom.com IP2012 / ip2022 data sheet 7.1.25 tctrl register timer 1 and 2 con guration. 7.1.26 xcfg register extra con guration bits for various functions. 76 5 4 32 1 0 00 t2ie t1ie 0 0 t2rst t1rst name description t2ie timer 2 interrupt enable 0 = timer 2 interrupt disabled 1 = timer 2 interrupt enabled t1ie timer 1 interrupt enable 0 = timer 1 interrupt disabled 1 = timer 1 interrupt enabled t2rst timer 2 reset bit. this bit always reads as z ero. 0 = writing 0 to this bit has no effect. 1 = writing 1 to this bit clears timer 2. t1rst timer 1 reset bit. this bit always reads as z ero. 0 = writing 0 to this bit has no effect. 1 = writing 1 to this bit clears timer 1. 76 5 4 3210 gie fwp r teos r t osc_en int_en rsvd fbusy name description gie global interrupt enable bit 0 = interrupts disabled 1 = interrupts enabled fwp flash write protect bit. this bit only affects operation of fwrite and ferase self-programming instructions on ash, not programming through the isd/isp interface. does not affect writes or erases of ram. 0 = writes to ash memory dis- abled (act as nop instructions) 1 = writes to ash memory enabled r teos real-time timer oversampling bit 0 = oversampling disabled 1 = oversampling enabled r t osc_en r tclk oscillator enable bit 0 = rtclk oscillator is operational 1 = rtclk oscillator turned off int_en int instruction interrupt enable bit 0 = int instructions only incre- ment the pc, like nop 1 = int instructions cause inter- r upts fbusy flash memory busy bit (read-only). f or more information about programming the ash memory, see section 4.7. 0 = flash memory is idle 1 = fetching instructions out of ash memory or busy process- ing an iread , ireadi , fwrite , fread or ferase instruction on flash
IP2012 / ip2022 data sheet www.ubicom.com 105 8.0 electrical characteristics 8.1 absolute maximum ratings (beyond which permanent damage may occur. correct operation not guar- anteed outside of dc speci cations in section 8.2) parameter minimum maximum units ambient temperature under bias -40 85 ? c storage temperature -65 150 ? c pqfp soldering temperature ramp to 160-180 ? c 2.5 ? c/sec pqfp soldering hold time at 160-180 ? c60 110 sec pqfp soldering temperature ramp from 160-180 ? c to 240 ? c maximum 3.0 ? c/sec pqfp soldering hold time at 240 ? c maximum 10 40 sec pqfp soldering temperature ramp down to 180 ? c5 ? c/sec v oltage on dvdd, xvdd, avdd, and gvdd with respect to vss -0.5 3.5 v v oltage on iovdd with respect to vss -0.5 4.5 v v oltage on port a through port f, osc1, rst , rtclk1, tsck, tsi, and tss inputs with respect to vss -0.5 5.7 v v oltage on port g inputs with respect to vss -0.5 3.5 v t otal power dissipation 1w maximum current out of all dvss pins 400 ma maximum current into all dvdd pins 400 ma maximum allowable sink current per i/o pin 160 ma maximum allowable source current per i/o pin (excluding port g) 160 ma maximum allowable source current per g pin 20 ma maximum allowable sink current per group of i/o pins between iovss pins 160 ma maximum allowable source current per group of i/o pins between iovdd pins (excluding port g) 160 ma latchup 200 ma ja , 80-pin pqfp package 48 ? c/w ja , 80-pin bga package 37 ? c/w flash block erase cycle lifetime (if using 20ms block erases - section 7.1.5) 20k cycles flash bulk erase cycle lifetime 20k cycles esd human body model - all pins 2000 v esd machine model - all pins 200 v
106 www.ubicom.com IP2012 / ip2022 data sheet 8.2 dc speci cations: ip2022-120, IP2012-120 operating temperature -40 ? c < ta < +85 ? c symbol parameter min typ max units conditions d vdd digital supply voltage 2.3 2.5 2.7 v a vdd analog supply voltage 2.3 2.5 2.7 v = dvdd ( lters between supplies) gvdd port g supply voltage 2.3 2.5 2.7 v = dvdd ( lters between supplies) xvdd pll supply voltage 2.3 2.5 2.7 v = dvdd ( lters between supplies) iovdd i/o supply voltage (except port g) > dvdd 2.5/3.3 3.6 v see note 4 idd supply current, full operation d vdd + avdd + gvdd + xvdd 150 ma dvdd = 2.3 - 2.7v, 120 mhz cpu core ex ecuting 100% of time (during isr and main program code) 70 ma dvdd = 2.5v, 120 mhz cpu core in isr only, 40mhz cpu core in main pro- gr am code (webserver application) iddio supply current, full operation iovdd only ma iovdd = dvdd - 3.6v no loads, no oating inputs isleep supply current, sleep d vdd + avdd + gvdd + xvdd 200 a dvdd = 2.7v, pll and oscillators off (xcfg bit 4 = 1, cmpcfg bit 7 = 0, adccfg bit 3 = 0, xcfg bit 0 = 0, fuse1 bit 3 = 0) isleepio supply current, sleep iovdd only a iovdd = 3.6v, pll and oscillators off, no loads, no oating inputs vih input high voltage, port a through port f 1.8 5.5 v dvdd = 2.3 - 2.7v, iovdd = dvdd - 3.6v input high voltage, osc1 and rtclk1 inputs 1.8 dvdd v input high voltage, rst , tsck, tsi, and tss inputs 2.25 5.5 v vil input low voltage, port a through port f 1.0 v dvdd = 2.3 - 2.7v, iovdd = dvdd - 3.6v input low voltage, osc1 and r tclk1 inputs 0.4 v input low voltage, rst , tsck, tsi, and tss inputs 0.9 v vina analog input voltage (port g) a vdd v see note 1 iil input leakage current for po rt a through port g, r tclk1, and tso pins -1 0.001 1 a port g = 0v or avdd (see note 1), r tclk1 = 0v or dvdd all other inputs = 0v or 5.5v tso measured while tss = 1 r tclk1 measured in sleep mode and fuse0 bit 14 = 1
IP2012 / ip2022 data sheet www.ubicom.com 107 1. if vref is used for the adc reference voltage (see section 5.7.1), then the maximum input voltage on a port g in- put is vref. 2. data in the typical (?typ?) column is at 2.5/3.3v, 25 ? c unless otherwise stated. 3. the port a through port f pins have a weak latch, even when the pin is con gured as an input, which drives oating i/o pins to 0v or to a diode drop below dvdd. some current is required to toggle the state of the latch. 4. if iovdd rises before dvdd, the IP2012 / ip2022 may drive the i/o pins to iovdd before dvdd has stabilized. however, there is an internal diode from dvdd to iovdd, so dvdd should never exceed iovdd. 5. these pins are guaranteed to pull up above their vih level, even if iovdd = dvdd = 2.3v. iil input leakage current for osc1 pin -1 10 a osc1 = 0v or dvdd osc1 measured in sleep mode and fuse0 bit 15 = 1 iil input pull-up/down leakage current for port a through po rt f pins -300 - 100 a see note 3. iilt input leakage current for rst , tsck, tsi, tss inputs -60 1 a vin = 0 to 5.5v. these pins have active internal pull-ups to a diode drop below iovdd. see note 5. (60kohm min., 103kohm typ., 173kohm max) ioh output high current from po rt a pins and re5, re6, rf1 and rf2 pins 24 60 96 ma voh = 2.4v iovdd = 3.0 to 3.6v output high current from po rt b pins and re4:0, re7, rf7:3, rf0, and tso pins 11 24 39 ma output high current from po rt c and port d pins 81829ma output high current from po rt g pins 41 22 4m av oh = 1.8v gvdd = 2.3 to 2.7v iol output low current from port a pins and re5, re6, rf1 and rf2 pins 25 40 50 ma vol = 0.4v iovdd = 3.0 to 3.6v output low current from port b pins and re4:0, re7, rf7:3, rf0, and tso pins 91624ma output low current from port c and port d pins 61115ma output low current from port g pins 41 32 4m av ol = 0.4v gvdd = 2.3 to 2.7v symbol parameter min typ max units conditions
108 www.ubicom.com IP2012 / ip2022 data sheet 8.3 dc speci cations: ip2022-160 operating temperature 0 ? c < ta < +55 ? c symbol parameter min typ max units conditions d vdd digital supply voltage 2.55 2.625 2.70 v a vdd analog supply voltage 2.55 2.625 2.70 v = dvdd ( lters between supplies) gvdd port g supply voltage 2.55 2.625 2.70 v = dvdd ( lters between supplies) xvdd pll supply voltage 2.55 2.625 2.70 v = dvdd ( lters between supplies) iovdd i/o supply voltage (except port g) > dvdd 2.625/ 3.3 3.6 v see note 4 idd supply current, full operation d vdd + avdd + gvdd + xvdd ma dvdd = 2.55 - 2.70v, 160 mhz cpu core executing 100% of time (during isr and main program code) ma dvdd = 2.625v, 160 mhz cpu core in isr only, 53.33mhz cpu core in main program code (webserver application) iddio supply current, full operation iovdd only ma iovdd = dvdd - 3.6v no loads, no oating inputs isleep supply current, sleep d vdd + avdd + gvdd + xvdd 200 a dvdd = 2.70v, pll and oscillators off (xcfg bit 4 = 1, cmpcfg bit 7 = 0, adccfg bit 3 = 0, xcfg bit 0 = 0, fuse1 bit 3 = 0) isleepio supply current, sleep iovdd only a iovdd = 3.6v, pll and oscillators off, no loads, no oating inputs vih input high voltage, port a through port f 1.8 5.5 v dvdd = 2.55 - 2.70v, iovdd = dvdd - 3.6v input high voltage, osc1 and rtclk1 inputs 1.8 dvdd v input high voltage, rst , tsck, tsi, and tss inputs 2.25 5.5 v vil input low voltage, port a through port f 1.0 v dvdd = 2.55 - 2.70v, iovdd = dvdd - 3.6v input low voltage, osc1 and r tclk1 inputs 0.4 v input low voltage, rst , tsck, tsi, and tss inputs 0.9 v vina analog input voltage (port g) a vdd v see note 1 iil input leakage current for po rt a through port g, r tclk1, and tso pins -1 0.001 1 a port g = 0v or avdd (see note 1), r tclk1 = 0v or dvdd all other inputs = 0v or 5.5v tso measured while tss = 1 r tclk1 measured in sleep mode and fuse0 bit 14 = 1
IP2012 / ip2022 data sheet www.ubicom.com 109 1. if vref is used for the adc reference voltage (see section 5.7.1), then the maximum input voltage on a port g in- put is vref. 2. data in the typical (?typ?) column is at 2.625/3.3v, 25 ? c unless otherwise stated. 3. the port a through port f pins have a weak latch, even when the pin is con gured as an input, which drives oating i/o pins to 0v or to a diode drop below dvdd. some current is required to toggle the state of the latch. 4. if iovdd rises before dvdd, the ip2022 may drive the i/o pins to iovdd before dvdd has stabilized. however, there is an internal diode from dvdd to iovdd, so dvdd should never exceed iovdd. 5. these pins are guaranteed to pull up above their vih level, even if iovdd = dvdd = 2.55v. iil input leakage current for osc1 pin -1 10 a osc1 = 0v or dvdd osc1 measured in sleep mode and fuse0 bit 15 = 1 iil input pull-up/down leakage current for port a through po rt f pins -80 - 80 a see note 3. iilt input leakage current for rst , tsck, tsi, tss inputs -60 1 a vin = 0 to 5.5v. these pins have active internal pull-ups to a diode drop below iovdd. see note 5. (60kohm min., 103kohm typ., 173kohm max) ioh output high current from po rt a pins and re5, re6, rf1 and rf2 pins 24 60 96 ma voh = 2.4v iovdd = 3.0 to 3.6v output high current from po rt b pins and re4:0, re7, rf7:3, rf0, and tso pins 11 24 39 ma output high current from po rt c and port d pins 81829ma output high current from po rt g pins 41 22 4m av oh = 1.8v gvdd = 2.55 to 2.70v iol output low current from port a pins and re5, re6, rf1 and rf2 pins 25 40 50 ma vol = 0.4v iovdd = 3.0 to 3.6v output low current from port b pins and re4:0, re7, rf7:3, rf0, and tso pins 91624ma output low current from port c and port d pins 61115ma output low current from port g pins 41 32 4m av ol = 0.4v gvdd = 2.55 to 2.70v symbol parameter min typ max units conditions
110 www.ubicom.com IP2012 / ip2022 data sheet 8.4 ac speci cations: ip2022-120, IP2012-120 operating temperature: -40 ? c < ta < +85 ? c 6. vdd must start rising from vss to ensure proper power-on-reset when relying on the internal power-on-reset circuitry. if power supply takes more than 50ms to rise from 0 to 2.5v, use rcs on rst pin (see figure 3-16). symbol parameter min typ max units conditions fcore cpu core clock frequency 0 120 mhz execution from program ram f ash cpu core clock frequency 0 40 mhz execution from program ash fsys system clock frequency 0 120 mhz f osc external clock frequency on osc1 0 120 mhz f oscr external clock frequency on rtclk1 0 120 mhz fxo crystal frequency, osc 4.75 4.8 5.0 mhz ext. crystal, 100 ppm fpll pll input frequency, after predivider 4.75 4.8 5.0 mhz trim0=fbfe fxr crystal frequency, rtclk 32.765 32.768 32.771 khz ext. 32.768 khz crystal, 100 ppm t osl, tosh clock in (osc1) low or high time 3 ns tr l, trh clock in (rtclk1) low or high time 3.5 ns svdd dvdd slew rate to ensure power-on reset 0.05 v/ms see note 6.
IP2012 / ip2022 data sheet www.ubicom.com 111 8.5 ac speci cations: ip2022-160 operating temperature: 0 ? c < ta < +55 ? c 7. vdd must start rising from vss to ensure proper power-on-reset when relying on the internal power-on-reset circuitry. if power supply takes more than 50ms to rise from 0 to 2.5v, use rcs on rst pin (see figure 3-16). 8. the 160mhz part is speci ed for everything the 120mhz part is speci ed for (except temperature range), and it will also run at 160mhz. cpu core clock and system clock frequencies between 120 and 160mhz are not guar- anteed, because the pll input frequency is only speci ed for 4.75?5mhz (with trim0=fbfe) to get a system clock up to 120mhz, or at 3.2mhz (with trim0=fbfd) to get 160mhz. see figure 3-18, and con gure fuse0, trim0, and fcfg correctly. typically customers who buy 160mhz parts will only use a 3.2mhz crystal, giving 3.2mhz into the pll, and a 160mhz system clock, with trim0=fbfd and fuse0 bits 15, 11, 10, and 9 = 0. symbol parameter min typ max units conditions fcore cpu core clock frequency 0 120 or 160 mhz execution from program ram. see note 8. f ash cpu core clock frequency 0 40 or 53.33 mhz execution from program ash. see note 8. fsys system clock frequency 0 120 or 160 mhz see note 8. f osc external clock frequency on osc1 0 120 mhz f oscr external clock frequency on r tclk1 0 120 mhz fxo crystal frequency, osc 3.2 mhz ext. crystal, 100 ppm. see note 8. fpll pll input frequency, after predivider 3.2 mhz trim0=fbfd. see note 8. fxr crystal frequency, rtclk 32.765 32.768 32.771 khz ext. crystal, 100 ppm t osl, tosh ext. clock in (osc1) low or high time 3 ns tr l, trh ext. clock in (rtclk1) low or high time 3.5 ns svdd dvdd slew rate to ensure power-on reset 0.05 v/ms see note 7.
112 www.ubicom.com IP2012 / ip2022 data sheet 8.6 comparator dc and ac speci cations operating temperature: ?40 ? c < ta < +85 ? c for ip2022-120 and IP2012-120; 0 ? c < ta < +55 ? c for ip2022-160. 8.7 adc 10-bit converter dc and ac speci cations vref = avdd, -40 ? c < ta < +85 ? c for ip2022-120, IP2012-120; 0 ? c < ta < +55 ? c for ip2022-160 parameter min typ max units conditions input offset voltage 10 25 mv cmpt2:0 bits in trim0 reg- ister are 111 hysteresis, rising or falling edge 20 50 80 mv bandwidth 15 mhz min. 100 mv peak-to-peak response time 100 ns voverdrive = 50 mv does not include compara- tor mode entry stabilization time time from enabling comparator until output is valid 2000 ns input voltage range 0.1 avdd - 0.1 v parameter min typ max units conditions sampling rate 48 khz conversion time 20.8 s differential nonlinearity error (dnl) 1.0 lsb integral nonlinearity error (inl) 1.25 lsb offset error 1.0 lsb full-scale error 1.0 lsb
IP2012 / ip2022 data sheet www.ubicom.com 113 9.0 package dimensions 9.1 pqfp 80-pin, 14 mm 20 mm 2.8 mm body, 0.8 mm pitch, 17.9 mm 23.9 mm tip-to-tip. all dimensions in mm. c c gauge plane pin
114 www.ubicom.com IP2012 / ip2022 data sheet 9.2 bga (available for ip2022-120 only) 80-pin, 9 mm 9 mm 0.95 mm body, 0.8 mm ball spacing ref. a a1 a2 d d1 dimensional reference d2 e e1 e2 b c aaa bbb ccc e f m n 0.80 0.90 10 80 0.80 bsc 8.80 0.39 9.00 0.44 0.25 7.20 bsc 0.12 0.10 0.10 1.00 9.20 0.49 9.00 9.00 9.00 9.20 9.20 9.20 8.80 8.80 8.80 0.65 0.70 0.75 0.21 0.26 0.31 1.11 1.21 1.31 min. nom. max. 7.20 bsc d 0.10 a b e d2 to p view bottom view (e1) e e (d1) 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k side view detail a detail b f f b 4 nx b 0.15 s s c c a b s s 0.075 detail a seating plane a2 a1 a c ccc c c c bbb 6 5 aaa c 1. all dimensins are in millimeters. 2. 'e' represents the basic solder ball pitch. 3. 'm' represents the basic solder ball matrix size, and symbol 'n' is the number of balls after depopulating. 4. 'b' is measureable at the maximum solder ball diameter after reflow parallel to primary datum - c - . 5. dimension 'aaa' is measured parallel to primary datum - c - . 6. primary datum - c - and seating plane are defined by the spherical crowns of the solder balls. 7. package surface shall be matte finish charmilles 24 to 27. 8. package centering to substrate shall be 0.0760mm maximum for both x and y direction respectively. 9. package warp shall be 0.050mm maximum. 10. substrate material base is bt resin. 1 1. the overall package thickness 'a' already considers collapse balls. 12. dimensioning and tolerancing per asme y14.5-1994.
IP2012 / ip2022 data sheet www.ubicom.com 115 10.0 part numbering ta b le 10-1 ordering information device pins i/o package program flash program ram data ram temperature IP2012/pq80-120 80 48 pqfp 64kbytes (32k x 16) 16kbytes (8k x 16) 4kbytes ?40 ? to 85 ? c ip2022/pq80-120 80 52 pqfp 64kbytes (32k x 16) 16kbytes (8k x 16) 4kbytes ?40 ? to 85 ? c ip2022/bg80-120 80 52 bga 64kbytes (32k x 16) 16kbytes (8k x 16) 4kbytes ?40 ? to 85 ? c ip2022/pq80-160 80 52 pqfp 64kbytes (32k x 16) 16kbytes (8k x 16) 4kbytes 0 ? to 55 ? c 515-013e.eps ip 2022 xx80 xxx /- mips rating package type, pq80 = 80-pin pqfp, bg80 = 80-pin ubga device number device family
ubicom, inc. develops and markets wireless network processor and software platforms that enable all electronic devices to be connected to each other ? securely, cost-effectively and transparently. with headquarters in mountain view, california, ubicom also has of ces in southern california as well as belgium, taiwan and hong kong. for more information, visit www.ubicom.com. copyright ? 2003 ubicom, inc. all rights reserved. ubicom, IP2012, ip2022, and ipmodule are trademarks of ubicom, inc. all other trademarks are the property of their respective holders. ip2k-dds-2000-17 (3/17/2003) 635 clyde avenue mountain view, ca 94043 t el: 650.210.1500 f ax: 650.210.8715 email: sales@ubicom.com w eb: www.ubicom.com sales and technical support contact information f or the latest contact and support information on ip devices, please visit the ubicom web site at www.ubicom.com. the site contains technical literature, local sales contacts, tech support, and many other features. the products are not authorized for use in life support systems or under conditions where failure of the product would endanger the life or safety of the user, except when prior written approval is obtained from ubicom, inc. ask your sales representive for details.

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